From d5ad4ce36c2a247e31f48a046ae976276e9bab07 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Tue, 4 Feb 2025 09:50:44 -0800 Subject: [PATCH] soc/intel/pantherlake: Add ability to set SaGv work points MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Hook up SaGv work point UPDs. BUG=none TEST=Boot to OS. Signed-off-by: Bora Guvendik Change-Id: Ie38d007edc293727066f2bc9f67037e6fbe77aa5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/86277 Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/chip.h | 8 ++++++++ src/soc/intel/pantherlake/romstage/fsp_params.c | 5 +++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h index e879fadb60..cd91e31dd0 100644 --- a/src/soc/intel/pantherlake/chip.h +++ b/src/soc/intel/pantherlake/chip.h @@ -42,6 +42,14 @@ struct ibecc_config { uint16_t region_mask[MAX_IBECC_REGIONS]; }; +/* SaGv gears */ +enum soc_intel_pantherlake_sagv_gears { + GEAR_AUTO = 0, + GEAR_1 = 1, + GEAR_2 = 2, + GEAR_4 = 4, +}; + enum soc_intel_pantherlake_power_limits { PTL_U_1_CORE, PTL_H_1_CORE, diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 5b968918b2..0c17d020c3 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -73,6 +73,11 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg, m_cfg->SaGvWpMask = config->sagv_wp_bitmap; else m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3; + + for (size_t i = 0; i < HOB_MAX_SAGV_POINTS; i++) { + m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i]; + m_cfg->SaGvGear[i] = config->sagv_gear[i]; + } } if (config->max_dram_speed_mts)