diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index e879fadb60..cd91e31dd0 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -42,6 +42,14 @@ struct ibecc_config {
 	uint16_t region_mask[MAX_IBECC_REGIONS];
 };
 
+/* SaGv gears */
+enum soc_intel_pantherlake_sagv_gears {
+	GEAR_AUTO = 0,
+	GEAR_1 = 1,
+	GEAR_2 = 2,
+	GEAR_4 = 4,
+};
+
 enum soc_intel_pantherlake_power_limits {
 	PTL_U_1_CORE,
 	PTL_H_1_CORE,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index 5b968918b2..0c17d020c3 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -73,6 +73,11 @@ static void fill_fspm_mrc_params(FSP_M_CONFIG *m_cfg,
 			m_cfg->SaGvWpMask = config->sagv_wp_bitmap;
 		else
 			m_cfg->SaGvWpMask = SAGV_POINTS_0_1_2_3;
+
+		for (size_t i = 0; i < HOB_MAX_SAGV_POINTS; i++) {
+			m_cfg->SaGvFreq[i] = config->sagv_freq_mhz[i];
+			m_cfg->SaGvGear[i] = config->sagv_gear[i];
+		}
 	}
 
 	if (config->max_dram_speed_mts)