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arm: libpayload: Make cache invalidation take pointers instead of integers

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This minor refactoring patch changes the signature of all limited cache
invalidation functions in Coreboot and libpayload from unsigned long to
void * for the address argument, since that's really what you have in
95% of the cases and I think it's ugly to have casting boilerplate all
over the place.

CQ-DEPEND=CL:167358
BUG=chrome-os-partner:21969
TEST=Make sure all payloads still compile cleanly when this and
dependent changes are in.

Change-Id: Ic9d3b2ea70b6aa8aea6647adae43ee2183b4e065
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167338
This commit is contained in:
Julius Werner 2013-08-28 14:43:14 -07:00 • committed by Caroline Tice
commit d550bec944
6 changed files with 22 additions and 22 deletions
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13
payloads/libpayload/arch/armv7/cache.c
View file

@ -213,16 +213,15 @@ static unsigned int line_bytes(void)
* perform cache maintenance on a particular memory range rather than the
* entire cache.
*/
static void dcache_op_mva(unsigned long addr,
unsigned long len, enum dcache_op op)
static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
{
unsigned long line, linesize;
linesize = line_bytes();
line = addr & ~(linesize - 1);
line = (uint32_t)addr & ~(linesize - 1);
dsb();
while (line < addr + len) {
while ((void *)line < addr + len) {
switch(op) {
case OP_DCCIMVAC:
dccimvac(line);
@ -241,17 +240,17 @@ static void dcache_op_mva(unsigned long addr,
isb();
}
void dcache_clean_by_mva(unsigned long addr, unsigned long len)
void dcache_clean_by_mva(void const *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCCMVAC);
}
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
void dcache_invalidate_by_mva(unsigned long addr, unsigned long len)
void dcache_invalidate_by_mva(void const *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCIMVAC);
}

7
payloads/libpayload/include/armv7/arch/cache.h
View file

@ -32,6 +32,7 @@
#ifndef ARMV7_CACHE_H
#define ARMV7_CACHE_H
#include <stddef.h>
#include <stdint.h>
/* SCTLR bits */
@ -290,13 +291,13 @@ static inline void write_sctlr(uint32_t val)
void dcache_clean_invalidate_all(void);
/* dcache clean by modified virtual address to PoC */
void dcache_clean_by_mva(unsigned long addr, unsigned long len);
void dcache_clean_by_mva(void const *addr, size_t len);
/* dcache clean and invalidate by modified virtual address to PoC */
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
/* dcache invalidate by modified virtual address to PoC */
void dcache_invalidate_by_mva(unsigned long addr, unsigned long len);
void dcache_invalidate_by_mva(void const *addr, size_t len);
void dcache_clean_all(void);

13
src/arch/armv7/cache.c
View file

@ -213,16 +213,15 @@ static unsigned int line_bytes(void)
* perform cache maintenance on a particular memory range rather than the
* entire cache.
*/
static void dcache_op_mva(unsigned long addr,
unsigned long len, enum dcache_op op)
static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op)
{
unsigned long line, linesize;
linesize = line_bytes();
line = addr & ~(linesize - 1);
line = (uint32_t)addr & ~(linesize - 1);
dsb();
while (line < addr + len) {
while ((void *)line < addr + len) {
switch(op) {
case OP_DCCIMVAC:
dccimvac(line);
@ -241,17 +240,17 @@ static void dcache_op_mva(unsigned long addr,
isb();
}
void dcache_clean_by_mva(unsigned long addr, unsigned long len)
void dcache_clean_by_mva(void const *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCCMVAC);
}
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len)
void dcache_clean_invalidate_by_mva(void const *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCCIMVAC);
}
void dcache_invalidate_by_mva(unsigned long addr, unsigned long len)
void dcache_invalidate_by_mva(void const *addr, size_t len)
{
dcache_op_mva(addr, len, OP_DCIMVAC);
}

7
src/arch/armv7/include/arch/cache.h
View file

@ -32,6 +32,7 @@
#ifndef ARMV7_CACHE_H
#define ARMV7_CACHE_H
#include <stddef.h>
#include <stdint.h>
/* SCTLR bits */
@ -290,13 +291,13 @@ static inline void write_sctlr(uint32_t val)
void dcache_clean_invalidate_all(void);
/* dcache clean by modified virtual address to PoC */
void dcache_clean_by_mva(unsigned long addr, unsigned long len);
void dcache_clean_by_mva(void const *addr, size_t len);
/* dcache clean and invalidate by modified virtual address to PoC */
void dcache_clean_invalidate_by_mva(unsigned long addr, unsigned long len);
void dcache_clean_invalidate_by_mva(void const *addr, size_t len);
/* dcache invalidate by modified virtual address to PoC */
void dcache_invalidate_by_mva(unsigned long addr, unsigned long len);
void dcache_invalidate_by_mva(void const *addr, size_t len);
void dcache_clean_all(void);

2
src/cpu/samsung/exynos5250/cpu.c
View file

@ -125,7 +125,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase,
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva(lower, upper - lower);
dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
printk(BIOS_DEBUG, "Initializing Exynos LCD.\n");

2
src/cpu/samsung/exynos5420/cpu.c
View file

@ -136,7 +136,7 @@ static void exynos_displayport_init(device_t dev, u32 lcdbase,
uint32_t lower = ALIGN_DOWN(lcdbase, MiB);
uint32_t upper = ALIGN_UP(lcdbase + fb_size, MiB);
dcache_clean_invalidate_by_mva(lower, upper - lower);
dcache_clean_invalidate_by_mva((void *)lower, upper - lower);
mmu_config_range(lower / MiB, (upper - lower) / MiB, DCACHE_OFF);
mmio_resource(dev, 1, lcdbase/KiB, (fb_size + KiB - 1)/KiB);