From d4bee96484dfe1fda8f983c0e088c29b4ad115c8 Mon Sep 17 00:00:00 2001 From: "Johann C. Rode" Date: Sat, 1 Nov 2025 13:54:32 -0700 Subject: [PATCH] mb/lenovo/sklkbl: refactor memory_init_params to use gpio_base2_value() Cosmetic fix validated on a Thinkpad T470s. Change-Id: I7e2032a665933cb7e002a7202bcd4305dfcdbed4 Signed-off-by: Johann C. Rode Reviewed-on: https://review.coreboot.org/c/coreboot/+/89864 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Paul Menzel --- .../lenovo/sklkbl_thinkpad/variant.h | 2 ++ .../variants/t470s/memory_init_params.c | 17 ++++++++++-- .../variants/t480s/memory_init_params.c | 27 ++++++++++++++----- 3 files changed, 37 insertions(+), 9 deletions(-) diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h index 66fdc0fa82..92255f2e0d 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variant.h +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variant.h @@ -5,6 +5,8 @@ void variant_config_gpios(void); +int variant_memory_sku(void); + void ssdt_add_dgpu(const struct device *dev); void dgpu_detect(void); diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c index 001e934b3a..cc9375808a 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t470s/memory_init_params.c @@ -6,6 +6,7 @@ #include #include #include +#include "../../variant.h" static const struct pad_config memory_id_gpio_table[] = { PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ @@ -15,6 +16,19 @@ static const struct pad_config memory_id_gpio_table[] = { PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ }; +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPP_F16, + GPP_F17, + GPP_F18, + GPP_F19, + GPP_F20, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { int spd_idx; @@ -29,8 +43,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* Get SPD for soldered RAM SPD (CH A) */ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); - spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | - gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; + spd_idx = variant_memory_sku(); printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx); mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size); diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c index 001e934b3a..3cbca9ae6c 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/t480s/memory_init_params.c @@ -6,15 +6,29 @@ #include #include #include +#include "../../variant.h" static const struct pad_config memory_id_gpio_table[] = { - PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ - PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ - PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ - PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ - PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ }; +int variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPP_F16, + GPP_F17, + GPP_F18, + GPP_F19, + GPP_F20, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { int spd_idx; @@ -29,8 +43,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd) /* Get SPD for soldered RAM SPD (CH A) */ gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); - spd_idx = gpio_get(GPP_F16) | gpio_get(GPP_F17) << 1 | gpio_get(GPP_F18) << 2 | - gpio_get(GPP_F19) << 3 | gpio_get(GPP_F20) << 4; + spd_idx = variant_memory_sku(); printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); snprintf(spd_name, sizeof(spd_name), "spd_%d.bin", spd_idx); mem_cfg->MemorySpdPtr00 = (uintptr_t)cbfs_map(spd_name, &spd_size);