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AMD Rev F support

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Yinghai Lu 2006-10-04 20:46:15 +00:00
commit d4b278c02c
130 changed files with 11666 additions and 655 deletions
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3
src/include/cpu/amd/microcode.h
View file

@ -2,4 +2,5 @@
#define CPU_AMD_MICORCODE_H
void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id);
#endif /* CPU_AMD_MICROCODE_H */
#endif /* CPU_AMD_MICROCODE_H */

42
src/include/cpu/amd/model_fxx_rev.h
View file

@ -1,5 +1,6 @@
#include <arch/cpu.h>
#if K8_REV_F_SUPPORT == 0
static inline int is_cpu_rev_a0(void)
{
return (cpuid_eax(1) & 0xfffef) == 0x0f00;
@ -74,5 +75,46 @@ static int is_e0_later_in_bsp(int nodeid)
int is_e0_later_in_bsp(int nodeid); //defined model_fxx_init.c
#endif
#endif
#if K8_REV_F_SUPPORT == 1
//AMD_F0_SUPPORT
static inline int is_cpu_pre_f0(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x40f00;
}
static inline int is_cpu_f0(void)
{
return (cpuid_eax(1) & 0xfff00) == 0x40f00;
}
static inline int is_cpu_pre_f2(void)
{
return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
}
#ifdef __ROMCC__
//AMD_F0_SUPPORT
static int is_cpu_f0_in_bsp(int nodeid)
{
uint32_t dword;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid, 3);
dword = pci_read_config32(dev, 0xfc);
return (dword & 0xfff00) == 0x40f00;
}
static int is_cpu_pre_f2_in_bsp(int nodeid)
{
uint32_t dword;
device_t dev;
dev = PCI_DEV(0, 0x18+nodeid, 3);
dword = pci_read_config32(dev, 0xfc);
return (dword & 0xfff0f) < 0x40f02;
}
#else
int is_cpu_f0_in_bsp(int nodeid); // defined in model_fxx_init.c
#endif
#endif

2
src/include/cpu/x86/mem.h
View file

@ -6,7 +6,7 @@ static inline void clear_memory(void *addr, unsigned long size)
{
asm volatile(
"cld \n\t"
"rep stosl\n\t"
"rep; stosl\n\t"
: /* No outputs */
: "a" (0), "D" (addr), "c" (size>>2)
);