From d4a759a068a4631d73f96a2e16f6f8ee878d1235 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 30 Aug 2024 10:43:33 -0600 Subject: [PATCH] mb/system76/mtl: darp10: Add TCSS configs Fixes using USB3 devices at USB3 speeds in all ports. This fix requires `EnableTcssCovTypeA`, which is not available in the coreboot FSP headers and not available upstream as Intel will not make a Client FSP release. Change-Id: I9bc6c5fc4c13bfa2e31ee1ce334b91e151373b6e Signed-off-by: Tim Crawford Reviewed-on: https://review.coreboot.org/c/coreboot/+/83696 Tested-by: build bot (Jenkins) Reviewed-by: Jeremy Soller --- .../mtl/variants/darp10/overridetree.cb | 21 ++++++++++++++++++- .../system76/mtl/variants/darp10/ramstage.c | 8 +++++++ 2 files changed, 28 insertions(+), 1 deletion(-) diff --git a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb index 56487395b9..8baa5560b9 100644 --- a/src/mainboard/system76/mtl/variants/darp10/overridetree.cb +++ b/src/mainboard/system76/mtl/variants/darp10/overridetree.cb @@ -5,7 +5,26 @@ chip soc/intel/meteorlake subsystemid 0x1558 0xa743 inherit device ref tbt_pcie_rp0 on end - device ref tcss_xhci on end + device ref tcss_xhci on + register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + # TCP2 is used as HDMI + # TCP3 is not used + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""TBT Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port0 on end + end + chip drivers/usb/acpi + register "desc" = ""USB Type-C"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + device ref tcss_usb3_port1 on end + end + end + end + end device ref tcss_dma0 on end device ref xhci on register "usb2_ports" = "{ diff --git a/src/mainboard/system76/mtl/variants/darp10/ramstage.c b/src/mainboard/system76/mtl/variants/darp10/ramstage.c index 276279484f..0e3baf2ad6 100644 --- a/src/mainboard/system76/mtl/variants/darp10/ramstage.c +++ b/src/mainboard/system76/mtl/variants/darp10/ramstage.c @@ -4,6 +4,14 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) { + // Enable TCP1 USB-A conversion + // BIT 0:3 is mapping to PCH XHCI USB2 port + // BIT 4:5 is reserved + // BIT 6 is orientational + // BIT 7 is enable + // TODO: Add to coreboot FSP headers as no Client FSP release will be made. + //params->EnableTcssCovTypeA[1] = 0x82; + // XXX: Enabling C10 reporting causes system to constantly enter and // exit opportunistic suspend when idle. params->PchEspiHostC10ReportEnable = 0;