From d46776f74111d9b0b213e344cca4649fdc342940 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Tue, 31 Dec 2024 21:40:19 -0500 Subject: [PATCH] mb/asus/p8x7x-series: Drop unused MRC devicetree setting Drop MRC setting usb3.hs_port_switch_mask that since commit ee126348726b ("nb/sandybridge,sb/bd82x6x: Configure USB from southbridge devicetree") mirrors xhci_switchable_ports and is no longer used separately. Change-Id: Ic1937461ab45f74f29521a8692629290bfd3c560 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/85821 Reviewed-by: Nicholas Chin Tested-by: build bot (Jenkins) --- src/mainboard/asus/p8x7x-series/devicetree.cb | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/mainboard/asus/p8x7x-series/devicetree.cb b/src/mainboard/asus/p8x7x-series/devicetree.cb index a54e6d8de8..fbff870c75 100644 --- a/src/mainboard/asus/p8x7x-series/devicetree.cb +++ b/src/mainboard/asus/p8x7x-series/devicetree.cb @@ -7,13 +7,6 @@ chip northbridge/intel/sandybridge register "max_mem_clock_mhz" = "800" register "spd_addresses" = "{0x50, 0x51, 0x52, 0x53}" - # 4 bit switch mask. 0=not switchable, 1=switchable - # Means once it's loaded the OS, it can swap ports - # from/to EHCI/xHCI. Z77 has four USB3 ports, so 0xf - register "usb3.hs_port_switch_mask" = "0xf" - # (The other 3 usb3.* settings can be set from nvram options, and so are set - # from runtime code) - device domain 0 on device ref peg10 on end # PCIEX16_1 device ref igd on end