UPSTREAM: src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: I868d34132ba40c314d76c5315f620d8a44d48983
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a566d7fbe
Original-Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18687
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454559
This commit is contained in:
Lee Leahy
chrome-bot
parent
e4fbfd4ec3
commit
d354460903
37 changed files with 472 additions and 253 deletions
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@ -33,14 +33,19 @@ extern const u32 cim_verb_data_size;
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extern const u32 pc_beep_verbs[];
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extern const u32 pc_beep_verbs_size;
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#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = ARRAY_SIZE(pc_beep_verbs); \
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#define AZALIA_ARRAY_SIZES const u32 pc_beep_verbs_size = \
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ARRAY_SIZE(pc_beep_verbs); \
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const u32 cim_verb_data_size = sizeof(cim_verb_data)
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#define AZALIA_PIN_CFG(codec, pin, val) \
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(((codec) << 28) | ((pin) << 20) | (0x71c << 8) | ((val) & 0xff)), \
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(((codec) << 28) | ((pin) << 20) | (0x71d << 8) | (((val) >> 8) & 0xff)), \
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(((codec) << 28) | ((pin) << 20) | (0x71e << 8) | (((val) >> 16) & 0xff)), \
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(((codec) << 28) | ((pin) << 20) | (0x71f << 8) | (((val) >> 24) & 0xff))
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#define AZALIA_PIN_CFG(codec, pin, val) \
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(((codec) << 28) | ((pin) << 20) | (0x71c << 8) \
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| ((val) & 0xff)), \
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(((codec) << 28) | ((pin) << 20) | (0x71d << 8) \
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| (((val) >> 8) & 0xff)), \
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(((codec) << 28) | ((pin) << 20) | (0x71e << 8) \
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| (((val) >> 16) & 0xff)), \
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(((codec) << 28) | ((pin) << 20) | (0x71f << 8) \
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| (((val) >> 24) & 0xff))
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#define AZALIA_SUBVENDOR(codec, val) \
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(((codec) << 28) | (0x01720 << 8) | ((val) & 0xff)), \
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@ -54,11 +54,13 @@ struct device_operations {
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void (*set_link)(device_t dev, unsigned int link);
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void (*reset_bus)(struct bus *bus);
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#if CONFIG_GENERATE_SMBIOS_TABLES
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int (*get_smbios_data)(device_t dev, int *handle, unsigned long *current);
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int (*get_smbios_data)(device_t dev, int *handle,
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unsigned long *current);
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void (*get_smbios_strings)(device_t dev, struct smbios_type11 *t);
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#endif
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#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
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unsigned long (*write_acpi_tables)(device_t dev, unsigned long start, struct acpi_rsdp *rsdp);
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unsigned long (*write_acpi_tables)(device_t dev, unsigned long start,
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struct acpi_rsdp *rsdp);
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void (*acpi_fill_ssdt_generator)(device_t dev);
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void (*acpi_inject_dsdt_generator)(device_t dev);
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const char *(*acpi_name)(device_t dev);
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@ -84,7 +86,7 @@ struct bus {
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ROMSTAGE_CONST struct device *dev; /* This bridge device */
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ROMSTAGE_CONST struct device *children; /* devices behind this bridge */
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ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */
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ROMSTAGE_CONST struct bus *next; /* The next bridge on this device */
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unsigned int bridge_ctrl; /* Bridge control register */
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uint16_t bridge_cmd; /* Bridge command register */
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unsigned char link_num; /* The index of this link */
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@ -126,7 +128,7 @@ struct device {
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unsigned int class; /* 3 bytes: (base, sub, prog-if) */
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unsigned int hdr_type; /* PCI header type */
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unsigned int enabled : 1; /* set if we should enable the device */
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unsigned int initialized : 1; /* set if we have initialized the device */
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unsigned int initialized : 1; /* 1 if we have initialized the device */
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unsigned int on_mainboard : 1;
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struct pci_irq_info pci_irq_info[4];
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u8 command;
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@ -205,7 +207,8 @@ device_t dev_find_lapic(unsigned int apic_id);
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int dev_count_cpu(void);
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device_t add_cpu_device(struct bus *cpu_bus, unsigned int apic_id, int enabled);
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void set_cpu_topology(device_t cpu, unsigned int node, unsigned int package, unsigned int core, unsigned int thread);
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void set_cpu_topology(device_t cpu, unsigned int node, unsigned int package,
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unsigned int core, unsigned int thread);
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#define amd_cpu_topology(cpu, node, core) \
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set_cpu_topology(cpu, node, 0, core, 0)
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@ -252,7 +255,8 @@ void scan_lpc_bus(device_t bus);
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fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE)
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#define reserved_ram_resource(dev, idx, basek, sizek) \
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fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE | IORESOURCE_RESERVE)
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fixed_mem_resource(dev, idx, basek, sizek, IORESOURCE_CACHEABLE \
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| IORESOURCE_RESERVE)
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#define bad_ram_resource(dev, idx, basek, sizek) \
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reserved_ram_resource((dev), (idx), (basek), (sizek))
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@ -271,7 +275,7 @@ u32 find_pci_tolm(struct bus *bus);
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ROMSTAGE_CONST struct device *dev_find_slot(unsigned int bus,
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unsigned int devfn);
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ROMSTAGE_CONST struct device *dev_find_next_pci_device(
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ROMSTAGE_CONST struct device *previous_dev);
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ROMSTAGE_CONST struct device *previous_dev);
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ROMSTAGE_CONST struct device *dev_find_slot_on_smbus(unsigned int bus,
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unsigned int addr);
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ROMSTAGE_CONST struct device *dev_find_slot_pnp(u16 port, u16 device);
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@ -21,8 +21,10 @@
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static inline bool offset_unit_id(bool is_sb_ht_chain)
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{
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bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
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return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY || is_sb_ht_chain);
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bool need_offset = (CONFIG_HT_CHAIN_UNITID_BASE != 1)
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|| (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20);
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return need_offset && (!CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY
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|| is_sb_ht_chain);
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}
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#endif /* DEVICE_HYPERTRANSPORT_DEF_H */
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@ -42,9 +42,12 @@ struct pci_bus_operations {
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uint8_t (*read8)(struct bus *pbus, int bus, int devfn, int where);
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uint16_t (*read16)(struct bus *pbus, int bus, int devfn, int where);
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uint32_t (*read32)(struct bus *pbus, int bus, int devfn, int where);
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void (*write8)(struct bus *pbus, int bus, int devfn, int where, uint8_t val);
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void (*write16)(struct bus *pbus, int bus, int devfn, int where, uint16_t val);
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void (*write32)(struct bus *pbus, int bus, int devfn, int where, uint32_t val);
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void (*write8)(struct bus *pbus, int bus, int devfn, int where,
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uint8_t val);
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void (*write16)(struct bus *pbus, int bus, int devfn, int where,
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uint16_t val);
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void (*write32)(struct bus *pbus, int bus, int devfn, int where,
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uint32_t val);
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};
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struct pci_driver {
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@ -23,7 +23,8 @@
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#define PCI_STATUS 0x06 /* 16 bits */
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#define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
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#define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
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#define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
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/* Support User Definable Features [obsolete] */
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#define PCI_STATUS_UDF 0x40
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#define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
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#define PCI_STATUS_PARITY 0x100 /* Detected parity error */
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#define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
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@ -82,11 +83,13 @@
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#define PCI_CARDBUS_CIS 0x28
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#define PCI_SUBSYSTEM_VENDOR_ID 0x2c
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#define PCI_SUBSYSTEM_ID 0x2e
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#define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
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/* Bits 31..11 are address, 10..1 reserved */
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#define PCI_ROM_ADDRESS 0x30
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#define PCI_ROM_ADDRESS_ENABLE 0x01
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#define PCI_ROM_ADDRESS_MASK (~0x7ffUL)
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#define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
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/* Offset of first capability list entry */
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#define PCI_CAPABILITY_LIST 0x34
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/* 0x35-0x3b are reserved */
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#define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
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@ -97,15 +100,18 @@
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/* Header type 1 (PCI-to-PCI bridges) */
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#define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
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#define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
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#define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
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#define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
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/* Highest bus number behind the bridge */
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#define PCI_SUBORDINATE_BUS 0x1a
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/* Latency timer for secondary interface */
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#define PCI_SEC_LATENCY_TIMER 0x1b
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#define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
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#define PCI_IO_LIMIT 0x1d
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#define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
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#define PCI_IO_RANGE_TYPE_16 0x00
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#define PCI_IO_RANGE_TYPE_32 0x01
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#define PCI_IO_RANGE_MASK ~0x0f
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#define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
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/* Secondary status register, only bit 14 used */
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#define PCI_SEC_STATUS 0x1e
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#define PCI_MEMORY_BASE 0x20 /* Memory range behind */
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#define PCI_MEMORY_LIMIT 0x22
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#define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
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@ -116,22 +122,26 @@
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#define PCI_PREF_RANGE_TYPE_32 0x00
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#define PCI_PREF_RANGE_TYPE_64 0x01
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#define PCI_PREF_RANGE_MASK ~0x0f
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#define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
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/* Upper half of prefetchable memory range */
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#define PCI_PREF_BASE_UPPER32 0x28
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#define PCI_PREF_LIMIT_UPPER32 0x2c
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#define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
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#define PCI_IO_LIMIT_UPPER16 0x32
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/* 0x34 same as for htype 0 */
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/* 0x35-0x3b is reserved */
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#define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
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/* Same as PCI_ROM_ADDRESS, but for htype 1 */
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#define PCI_ROM_ADDRESS1 0x38
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/* 0x3c-0x3d are same as for htype 0 */
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#define PCI_BRIDGE_CONTROL 0x3e
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#define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
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/* Enable parity detection on secondary interface */
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#define PCI_BRIDGE_CTL_PARITY 0x01
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#define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
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#define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
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#define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
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#define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
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#define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
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#define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
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/* Fast Back2Back enabled on secondary interface */
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#define PCI_BRIDGE_CTL_FAST_BACK 0x80
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/* Header type 2 (CardBus bridges) */
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#define PCI_CB_CAPABILITY_LIST 0x14
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@ -156,19 +166,23 @@
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#define PCI_CB_IO_RANGE_MASK ~0x03
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/* 0x3c-0x3d are same as for htype 0 */
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#define PCI_CB_BRIDGE_CONTROL 0x3e
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#define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
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/* Similar to standard bridge control register */
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#define PCI_CB_BRIDGE_CTL_PARITY 0x01
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#define PCI_CB_BRIDGE_CTL_SERR 0x02
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#define PCI_CB_BRIDGE_CTL_ISA 0x04
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#define PCI_CB_BRIDGE_CTL_VGA 0x08
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#define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
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#define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
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#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
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/* Enable interrupt for 16-bit cards */
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#define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80
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/* Prefetch enable for both memory regions */
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100
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#define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
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#define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
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#define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
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#define PCI_CB_SUBSYSTEM_ID 0x42
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#define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
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/* 16-bit PC Card legacy mode base address (ExCa) */
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#define PCI_CB_LEGACY_MODE_BASE 0x44
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/* 0x48-0x7f reserved */
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/* Capability lists */
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@ -223,7 +237,8 @@
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#define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
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#define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
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#define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
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#define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
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/* Bus power/clock control enable (??) */
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#define PCI_PM_BPCC_ENABLE 0x80
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#define PCI_PM_DATA_REGISTER 7 /* (??) */
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#define PCI_PM_SIZEOF 8
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@ -232,7 +247,8 @@
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#define PCI_AGP_VERSION 2 /* BCD version number */
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#define PCI_AGP_RFU 3 /* Rest of capability flags */
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#define PCI_AGP_STATUS 4 /* Status register */
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#define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
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/* Maximum number of requests - 1 */
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#define PCI_AGP_STATUS_RQ_MASK 0xff000000
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#define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
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#define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
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#define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
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@ -240,10 +256,13 @@
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#define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
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#define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
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#define PCI_AGP_COMMAND 8 /* Control register */
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#define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
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/* Master: Maximum number of requests */
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#define PCI_AGP_COMMAND_RQ_MASK 0xff000000
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#define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
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#define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
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#define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
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/* Allow processing of AGP transactions */
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#define PCI_AGP_COMMAND_AGP 0x0100
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/* Allow processing of 64-bit addresses */
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#define PCI_AGP_COMMAND_64BIT 0x0020
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#define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
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#define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
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#define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
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@ -253,7 +272,8 @@
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/* Slot Identification */
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#define PCI_SID_ESR 2 /* Expansion Slot Register */
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#define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
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/* Number of expansion slots available */
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#define PCI_SID_ESR_NSLOTS 0x1f
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#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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@ -266,7 +286,8 @@
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#define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
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#define PCI_MSI_RFU 3 /* Rest of capability flags */
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#define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
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#define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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/* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
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#define PCI_MSI_ADDRESS_HI 8
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#define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
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#define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
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#define PCI_MSI_MASK_BIT 16 /* Mask bits register */
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@ -296,24 +317,30 @@
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#define PCI_X_STATUS_64BIT 0x00010000 /* 64-bit device */
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#define PCI_X_STATUS_133MHZ 0x00020000 /* 133 MHz capable */
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#define PCI_X_STATUS_SPL_DISC 0x00040000 /* Split Completion Discarded */
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#define PCI_X_STATUS_UNX_SPL 0x00080000 /* Unexpected Split Completion */
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/* Unexpected Split Completion */
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#define PCI_X_STATUS_UNX_SPL 0x00080000
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#define PCI_X_STATUS_COMPLEX 0x00100000 /* Device Complexity */
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#define PCI_X_STATUS_MAX_READ 0x00600000 /* Designed Max Memory Read Count */
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#define PCI_X_STATUS_MAX_SPLIT 0x03800000 /* Designed Max Outstanding Split Transactions */
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#define PCI_X_STATUS_MAX_CUM 0x1c000000 /* Designed Max Cumulative Read Size */
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#define PCI_X_STATUS_SPL_ERR 0x20000000 /* Rcvd Split Completion Error Msg */
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/* Designed Max Memory Read Count */
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#define PCI_X_STATUS_MAX_READ 0x00600000
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/* Designed Max Cumulative Read Size */
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#define PCI_X_STATUS_MAX_SPLIT 0x03800000
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/* Rcvd Split Completion Error Msg */
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#define PCI_X_STATUS_SPL_ERR 0x20000000
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#define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
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#define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
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/* PCI-X bridge registers */
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#define PCI_X_SEC_STATUS 2 /* Secondary status */
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#define PCI_X_SSTATUS_64BIT 0x0001 /* The bus behind the bridge is 64bits wide */
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#define PCI_X_SSTATUS_133MHZ 0x0002 /* The bus behind the bridge is 133Mhz Capable */
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/* The bus behind the bridge is 64bits wide */
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#define PCI_X_SSTATUS_64BIT 0x0001
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/* The bus behind the bridge is 133Mhz Capable */
|
||||
#define PCI_X_SSTATUS_133MHZ 0x0002
|
||||
#define PCI_X_SSTATUS_SPL_DISC 0x0004 /* Split Completion Discarded */
|
||||
#define PCI_X_SSTATUS_UNX_SPL 0x0008 /* Unexpected Split Completion */
|
||||
#define PCI_X_SSTATUS_SPL_OVR 0x0010 /* Split Completion Overrun */
|
||||
#define PCI_X_SSTATUS_SPL_DLY 0x0020 /* Split Completion Delayed */
|
||||
#define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6) /* PCI-X mode and frequency */
|
||||
/* PCI-X mode and frequency */
|
||||
#define PCI_X_SSTATUS_MFREQ(x) (((x) & 0x03c0) >> 6)
|
||||
#define PCI_X_SSTATUS_CONVENTIONAL_PCI 0x0
|
||||
#define PCI_X_SSTATUS_MODE1_66MHZ 0x1
|
||||
#define PCI_X_SSTATUS_MODE1_100MHZ 0x2
|
||||
|
|
@ -325,8 +352,10 @@
|
|||
#define PCI_X_SSTATUS_MODE2_533MHZ_REF_100MHZ 0xe
|
||||
#define PCI_X_SSTATUS_MODE2_533MHZ_REF_133MHZ 0xf
|
||||
#define PCI_X_SSTATUS_VERSION(x) (((x) >> 12) & 3) /* Version */
|
||||
#define PCI_X_SSTATUS_266MHZ 0x4000 /* The bus behind the bridge is 266Mhz Capable */
|
||||
#define PCI_X_SSTAUTS_533MHZ 0x8000 /* The bus behind the bridge is 533Mhz Capable */
|
||||
/* The bus behind the bridge is 266Mhz Capable */
|
||||
#define PCI_X_SSTATUS_266MHZ 0x4000
|
||||
/* The bus behind the bridge is 533Mhz Capable */
|
||||
#define PCI_X_SSTAUTS_533MHZ 0x8000
|
||||
|
||||
/* PCI Express capability registers */
|
||||
|
||||
|
|
|
|||
|
|
@ -21,7 +21,7 @@
|
|||
#include <device/device.h>
|
||||
|
||||
#define EHCI_BAR_INDEX 0x10
|
||||
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
|
||||
#define PCI_EHCI_CLASSCODE 0x0c0320 /* USB2.0 with EHCI controller */
|
||||
|
||||
pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx);
|
||||
u8 *pci_ehci_base_regs(pci_devfn_t dev);
|
||||
|
|
|
|||
|
|
@ -35,7 +35,8 @@ struct pci_data {
|
|||
};
|
||||
|
||||
struct rom_header *pci_rom_probe(struct device *dev);
|
||||
struct rom_header *pci_rom_load(struct device *dev, struct rom_header *rom_header);
|
||||
struct rom_header *pci_rom_load(struct device *dev,
|
||||
struct rom_header *rom_header);
|
||||
|
||||
unsigned long
|
||||
pci_rom_write_acpi_tables(struct device *device,
|
||||
|
|
|
|||
|
|
@ -11,7 +11,8 @@
|
|||
#define IORESOURCE_IRQ 0x00000400
|
||||
#define IORESOURCE_DRQ 0x00000800
|
||||
|
||||
#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM | IORESOURCE_IRQ | IORESOURCE_DRQ)
|
||||
#define IORESOURCE_TYPE_MASK (IORESOURCE_IO | IORESOURCE_MEM \
|
||||
| IORESOURCE_IRQ | IORESOURCE_DRQ)
|
||||
|
||||
#define IORESOURCE_PREFETCH 0x00001000 /* No side effects */
|
||||
#define IORESOURCE_READONLY 0x00002000
|
||||
|
|
@ -19,14 +20,18 @@
|
|||
#define IORESOURCE_RANGELENGTH 0x00008000
|
||||
#define IORESOURCE_SHADOWABLE 0x00010000
|
||||
#define IORESOURCE_BUS_HAS_VGA 0x00020000
|
||||
#define IORESOURCE_SUBTRACTIVE 0x00040000 /* This resource filters all of the unclaimed transactions
|
||||
* to the bus below.
|
||||
*/
|
||||
#define IORESOURCE_BRIDGE 0x00080000 /* The IO resource has a bus below it. */
|
||||
#define IORESOURCE_RESERVE 0x10000000 /* The resource needs to be reserved in the coreboot table */
|
||||
#define IORESOURCE_STORED 0x20000000 /* The IO resource assignment has been stored in the device */
|
||||
#define IORESOURCE_ASSIGNED 0x40000000 /* An IO resource that has been assigned a value */
|
||||
#define IORESOURCE_FIXED 0x80000000 /* An IO resource the allocator must not change */
|
||||
/* This resource filters all of the unclaimed transactions to the bus below. */
|
||||
#define IORESOURCE_SUBTRACTIVE 0x00040000
|
||||
/* The IO resource has a bus below it. */
|
||||
#define IORESOURCE_BRIDGE 0x00080000
|
||||
/* The resource needs to be reserved in the coreboot table */
|
||||
#define IORESOURCE_RESERVE 0x10000000
|
||||
/* The IO resource assignment has been stored in the device */
|
||||
#define IORESOURCE_STORED 0x20000000
|
||||
/* An IO resource that has been assigned a value */
|
||||
#define IORESOURCE_ASSIGNED 0x40000000
|
||||
/* An IO resource the allocator must not change */
|
||||
#define IORESOURCE_FIXED 0x80000000
|
||||
|
||||
/* PCI specific resource bits (IORESOURCE_BITS) */
|
||||
#define IORESOURCE_PCI64 (1<<0) /* 64bit long pci resource */
|
||||
|
|
@ -62,9 +67,11 @@ extern struct resource *new_resource(struct device *dev, unsigned int index);
|
|||
extern struct resource *find_resource(struct device *dev, unsigned int index);
|
||||
extern resource_t resource_end(struct resource *resource);
|
||||
extern resource_t resource_max(struct resource *resource);
|
||||
extern void report_resource_stored(struct device *dev, struct resource *resource, const char *comment);
|
||||
extern void report_resource_stored(struct device *dev,
|
||||
struct resource *resource, const char *comment);
|
||||
|
||||
typedef void (*resource_search_t)(void *gp, struct device *dev, struct resource *res);
|
||||
typedef void (*resource_search_t)(void *gp, struct device *dev,
|
||||
struct resource *res);
|
||||
extern void search_bus_resources(struct bus *bus,
|
||||
unsigned long type_mask, unsigned long type,
|
||||
resource_search_t search, void *gp);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue