UPSTREAM: src/include: Wrap lines at 80 columns
Fix the following warning detected by checkpatch.pl:
WARNING: line over 80 characters
Changed a few comments to reduce line length. File
src/include/cpu/amd/vr.h was skipped.
TEST=Build and run on Galileo Gen2
Change-Id: I868d34132ba40c314d76c5315f620d8a44d48983
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6a566d7fbe
Original-Change-Id: Ie3c07111acc1f89923fb31135684a6d28a505b61
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://review.coreboot.org/18687
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/454559
This commit is contained in:
Lee Leahy
chrome-bot
parent
e4fbfd4ec3
commit
d354460903
37 changed files with 472 additions and 253 deletions
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@ -40,7 +40,8 @@ struct amdfam10_sysconf_t {
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unsigned int nodes;
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unsigned int ht_c_num; // we only can have 32 ht chain at most
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unsigned int ht_c_conf_bus[HC_NUMS]; // 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
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// 4-->32: 4:segn, 8:bus_max, 8:bus_min, 4:linkn, 6: nodeid, 2: enable
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unsigned int ht_c_conf_bus[HC_NUMS];
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unsigned int io_addr_num;
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unsigned int conf_io_addr[HC_NUMS];
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unsigned int conf_io_addrx[HC_NUMS];
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@ -50,7 +51,8 @@ struct amdfam10_sysconf_t {
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unsigned int segbit;
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unsigned int hcdn_reg[HC_NUMS]; // it will be used by get_pci1234
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msr_t msr_pstate[NODE_NUMS * 5]; // quad cores all cores in one node should be the same, and p0,..p5
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// quad cores all cores in one node should be the same, and p0,..p5
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msr_t msr_pstate[NODE_NUMS * 5];
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unsigned int needs_update_pstate_msrs;
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unsigned int bsp_apicid;
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@ -78,10 +78,14 @@
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#define GL1_PCI 4
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#define GL1_FG 5
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#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx - To get on GeodeLink one bit has to be set */
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/* 1000xxxx - To get on GeodeLink one bit has to be set */
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#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28))
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#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
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#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
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#define MSR_CPU (GL0_CPU << 29) /* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't need to be routed */
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/* 6000xxxx - this is not used for BIOS since code executing on CPU doesn't
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* need to be routed
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*/
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#define MSR_CPU (GL0_CPU << 29)
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#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
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#define MSR_GP (GL0_GP << 29) /* A000xxxx */
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#define MSR_DF (GL0_DF << 29) /* C000xxxx */
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@ -293,7 +297,7 @@
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#define RSTPLL_UPPER_VDIV_SHIFT 6
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#define RSTPLL_UPPER_FBDIV_SHIFT 0
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#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
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#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
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#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F<<RSTPLL_LOWER_SWFLAGS_SHIFT)
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#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
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#define RSTPPL_LOWER_BYPASS_SHIFT 15
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#define RSTPPL_LOWER_TST_SHIFT 11
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@ -392,15 +396,23 @@
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#define MAX_COL_ADDR 17
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/* more fun stuff */
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#define BM 1 /* Base Mask - map power of 2 size aligned region */
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/* Base Mask - map power of 2 size aligned region */
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#define BM 1
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#define BMO 2 /* BM with an offset */
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#define R 3 /* Range - 4k range minimum */
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#define RO 4 /* R with offset */
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#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
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/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
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#define SC 5
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#define BMIO 6 /* Base Mask IO */
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#define SCIO 7 /* Swiss 0xCeese IO */
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#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU */
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#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU */
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/* Special marker for Shadow SC descriptors so setShadow proc is independent
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* of CPU
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*/
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#define SC_SHADOW 8
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/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent
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* of CPU
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*/
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#define R_SYSMEM 9
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#define BMO_SMM 10 /* Special marker for SMM */
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#define BM_SMM 11 /* Special marker for SMM */
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#define BMO_DMM 12 /* Special marker for DMM */
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@ -415,33 +427,33 @@
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/* Set up desc addresses from 20 - E8 */
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/* This is chip specific! */
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//remove after MSRINIT is gone
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#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */
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#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */
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#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
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#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */
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#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */
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#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */
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#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
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#define MSR_GLIU0_SYSMEM (MSR_GLIU0 + 0x28) /* RO should only be R */
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#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */
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#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */
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#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */
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#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */
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#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */
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#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */
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#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2D) /* SCO should only be SC */
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#define MSR_GLIU1_SYSMEM (MSR_GLIU1 + 0x29) /* RO should only be R */
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#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */
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#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */
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#define GLIU0_P2D_BM_0 (MSR_GLIU0 + 0x20) /* BASE1 */
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#define GLIU0_P2D_BM_1 (MSR_GLIU0 + 0x21) /* BASE2 */
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#define GLIU0_P2D_BM_2 (MSR_GLIU0 + 0x22)
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#define GLIU0_P2D_BM_3 (MSR_GLIU0 + 0x23)
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#define GLIU0_P2D_BM_4 (MSR_GLIU0 + 0x24)
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#define GLIU0_P2D_BM_5 (MSR_GLIU0 + 0x25)
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#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */
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#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */
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#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26) /* SMM */
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#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27) /* DMM */
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#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */
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#define GLIU0_P2D_R_0 (MSR_GLIU0 + 0x28) /* SYSMEM */
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#define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29)
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#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
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#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
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#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */
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#define GLIU0_P2D_SC_0 (MSR_GLIU0 + 0x2C) /* SHADOW */
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#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
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#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
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@ -454,28 +466,28 @@
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#define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7)
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#define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8)
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#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */
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#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */
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#define GLIU1_P2D_BM_0 (MSR_GLIU1 + 0x20) /* BASE1 */
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#define GLIU1_P2D_BM_1 (MSR_GLIU1 + 0x21) /* BASE2 */
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#define GLIU1_P2D_BM_2 (MSR_GLIU1 + 0x22)
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#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */
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#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */
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#define GLIU1_P2D_BM_3 (MSR_GLIU1 + 0x23) /* SMM */
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#define GLIU1_P2D_BM_4 (MSR_GLIU1 + 0x24) /* DMM */
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#define GLIU1_P2D_BM_5 (MSR_GLIU1 + 0x25)
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#define GLIU1_P2D_BM_6 (MSR_GLIU1 + 0x26)
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#define GLIU1_P2D_BM_7 (MSR_GLIU1 + 0x27)
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#define GLIU1_P2D_BM_8 (MSR_GLIU1 + 0x28)
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#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */
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#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x29) /* SYSMEM */
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#define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2A)
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#define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2B)
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#define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2C)
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#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */
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#define GLIU1_P2D_SC_0 (MSR_GLIU1 + 0x2D) /* SHADOW */
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#define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0)
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#define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1)
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#define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2)
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#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */
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#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3) /* FooGlue F0 for FPU */
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#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
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#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
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#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
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@ -483,21 +495,22 @@
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#define GLIU1_IOD_SC_5 (MSR_GLIU1 + 0xE8)
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/* definitions that are "once you are mostly up, start VSA" type things */
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#define SMM_OFFSET 0x40400000
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#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
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#define DMM_OFFSET 0x0C0000000
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#define DMM_SIZE 128
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#define FB_OFFSET 0x41000000
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#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
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#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
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#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
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#define SMM_OFFSET 0x40400000
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#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
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#define DMM_OFFSET 0x0C0000000
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#define DMM_SIZE 128
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#define FB_OFFSET 0x41000000
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#define PCI_MEM_TOP 0x0EFFFFFFF /* Top of PCI mem allocation region */
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#define PCI_IO_TOP 0x0EFFF /* Top of PCI I/O allocation region */
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#define END_OPTIONROM_SPACE 0x0DFFF /* E0000 is reserved for SystemROMs */
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#define MDD_SMBUS 0x06000 /* SMBUS IO location */
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#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
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#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
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#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
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#define ACPI_BASE 0x09C00 /* ACPI Base */
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#define MDD_PM 0x09D00 /* Power Management Logic - placed at the end of ACPI */
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#define MDD_SMBUS 0x06000 /* SMBUS IO location */
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#define MDD_GPIO 0x06100 /* GPIO & ICF IO location */
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#define MDD_MFGPT 0x06200 /* General Purpose Timers IO location */
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#define MDD_IRQ_MAPPER 0x06300 /* IRQ Mapper */
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#define ACPI_BASE 0x09C00 /* ACPI Base */
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/* Power Management Logic - placed at the end of ACPI */
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#define MDD_PM 0x09D00
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#define CS5535_IDSEL 0x02000000 /* IDSEL = AD25, device #15 */
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#define CHIPSET_DEV_NUM 15
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@ -21,19 +21,20 @@
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#ifndef CPU_AMD_LXDEF_H
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#define CPU_AMD_LXDEF_H
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#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/
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#define CPU_ID_2_0 0x000005A1
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#define CPU_ID_3_0 0x000005A2
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/* Stepping ID 1.x CPUbug fix to change it to 5A0*/
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#define CPU_ID_1_X 0x00000560
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#define CPU_ID_2_0 0x000005A1
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#define CPU_ID_3_0 0x000005A2
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#define CPU_REV_1_0 0x010
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#define CPU_REV_1_1 0x011
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#define CPU_REV_2_0 0x020
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#define CPU_REV_2_1 0x021
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#define CPU_REV_2_2 0x022
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#define CPU_REV_C_0 0x030
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#define CPU_REV_C_1 0x031
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#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/
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#define CPU_REV_C_3 0x033
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#define CPU_REV_1_0 0x010
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#define CPU_REV_1_1 0x011
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#define CPU_REV_2_0 0x020
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#define CPU_REV_2_1 0x021
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#define CPU_REV_2_2 0x022
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#define CPU_REV_C_0 0x030
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#define CPU_REV_C_1 0x031
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#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/
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#define CPU_REV_C_3 0x033
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/* MSR routing as follows*/
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@ -59,19 +60,23 @@
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#define GL1_AES 6
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#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28)) /* 1000xxxx, To get on GeodeLink one bit has to be set */
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/* 1000xxxx, To get on GeodeLink one bit has to be set */
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#define MSR_GLIU0 ((GL0_GLIU0 << 29) + (1 << 28))
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#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
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#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
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#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/
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/* 0000xxxx this is not used for BIOS since code executing on CPU doesn't
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* need to be routed
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*/
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#define MSR_CPU (GL0_CPU << 29)
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#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
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#define MSR_GP (GL0_GP << 29) /* A000xxxx */
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#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
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#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
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#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
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#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
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#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
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#define MSR_FG MSR_GLCP
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#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
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#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
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#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
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#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
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#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
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#define MSR_FG MSR_GLCP
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/*GeodeLink Interface Unit 0 (GLIU0) port0*/
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@ -168,9 +173,9 @@
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#define CPU_GLD_MSR_DIAG 0x2005
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#define DIAG_SEL1_MODE_SHIFT 16
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#define DIAG_SEL1_SET (1 << 31)
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#define DIAG_SEL1_SET (1 << 31)
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#define DIAG_SEL0__MODE_SHIFT 0
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#define DIAG_SET0_SET (1 << 15)
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#define DIAG_SET0_SET (1 << 15)
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#define CPU_PF_CONF 0x1100
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#define RETURN_STACK_ENABLE_SET (1 << 4)
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@ -207,13 +212,13 @@
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#define IM_CONFIG_LOWER_ICD_SET (1 << 8)
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#define IM_CONFIG_LOWER_EBE_SET (1 << 10)
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#define IM_CONFIG_LOWER_ABSE_SET (1 << 11)
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#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
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#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
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#define CPU_IC_INDEX 0x1710
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#define CPU_IC_DATA 0x1711
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#define CPU_IC_TAG 0x1712
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#define CPU_IC_DATA 0x1711
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#define CPU_IC_TAG 0x1712
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#define CPU_IC_TAG_I 0x1713
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#define CPU_ITB_INDEX 0x1720
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#define CPU_ITB_LRU 0x1721
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#define CPU_ITB_LRU 0x1721
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#define CPU_ITB_ENTRY 0x1722
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#define CPU_ITB_ENTRY_I 0x1723
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#define CPU_IM_BIST_TAG 0x1730
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@ -313,7 +318,7 @@
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#define CPU_BC_MSS_ARRAY_CTL2 0x1983
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#define CPU_FPU_MSR_MODE 0x1A00
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#define FPU_IE_SET (1 << 0)
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#define FPU_IE_SET (1 << 0)
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#define CPU_FP_UROM_BIST 0x1A03
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@ -386,13 +391,15 @@
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#define RSTPLL_UPPER_CPUMULT_SHIFT 1
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#define RSTPLL_UPPER_CPUDIV_SHIFT 0
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#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
|
||||
#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
|
||||
#define RSTPLL_LOWER_SWFLAGS_MASK \
|
||||
(0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
|
||||
#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
|
||||
#define RSTPPL_LOWER_COREBYPASS_SHIFT 12
|
||||
#define RSTPPL_LOWER_GLBYPASS_SHIFT 11
|
||||
#define RSTPPL_LOWER_PCISPEED_SHIFT 7
|
||||
#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1
|
||||
#define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
|
||||
#define RSTPLL_LOWER_BOOTSTRAP_MASK \
|
||||
(0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
|
||||
|
||||
#define RSTPPL_LOWER_GLLOCK_SET (1 << 25)
|
||||
#define RSTPPL_LOWER_CORELOCK_SET (1 << 24)
|
||||
|
|
@ -489,13 +496,13 @@
|
|||
#define GLPCI_ExtMSR (MSR_PCI + 0x201E)
|
||||
|
||||
#define GLPCI_SPARE (MSR_PCI + 0x201F)
|
||||
#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
|
||||
#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
|
||||
#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
|
||||
#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
|
||||
#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
|
||||
#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
|
||||
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
|
||||
#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
|
||||
#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
|
||||
#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
|
||||
#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
|
||||
#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
|
||||
#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
|
||||
#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
|
||||
|
||||
|
||||
|
||||
|
|
@ -522,15 +529,23 @@
|
|||
#define MAX_COL_ADDR 17
|
||||
|
||||
/* GLIU typedefs */
|
||||
#define BM 1 /* Base Mask - map power of 2 size aligned region*/
|
||||
/* Base Mask - map power of 2 size aligned region*/
|
||||
#define BM 1
|
||||
#define BMO 2 /* BM with an offset*/
|
||||
#define R 3 /* Range - 4k range minimum*/
|
||||
#define RO 4 /* R with offset*/
|
||||
#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
|
||||
/* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R*/
|
||||
#define SC 5
|
||||
#define BMIO 6 /* Base Mask IO*/
|
||||
#define SCIO 7 /* Swiss 0xCeese IO*/
|
||||
#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independent of CPU*/
|
||||
#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independent of CPU*/
|
||||
/* Special marker for Shadow SC descriptors so setShadow proc is independent
|
||||
* of CPU
|
||||
*/
|
||||
#define SC_SHADOW 8
|
||||
/* Special marker for SYSMEM R descriptors so GLIUInit proc is independent
|
||||
* of CPU
|
||||
*/
|
||||
#define R_SYSMEM 9
|
||||
#define BMO_SMM 10 /* Special marker for SMM*/
|
||||
#define BM_SMM 11 /* Special marker for SMM*/
|
||||
#define BMO_DMM 12 /* Special marker for DMM*/
|
||||
|
|
@ -566,7 +581,8 @@
|
|||
#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
|
||||
#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
|
||||
|
||||
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC*/
|
||||
/* SCO should only be SC*/
|
||||
#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C)
|
||||
|
||||
#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
|
||||
#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
|
||||
|
|
@ -612,12 +628,13 @@
|
|||
#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
|
||||
#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
|
||||
#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
|
||||
#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU*/
|
||||
/* FooGlue F0 for FPU*/
|
||||
#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0)
|
||||
|
||||
/* ------------------------ */
|
||||
|
||||
#define SMM_OFFSET 0x80400000 /* above 2GB */
|
||||
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
|
||||
#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
|
||||
|
||||
/* DRAM_TERMINATED affects how the DELAY register is set. */
|
||||
#define DRAM_TERMINATED 'T'
|
||||
|
|
|
|||
|
|
@ -77,7 +77,8 @@ static inline int is_e0_later_in_bsp(int nodeid)
|
|||
if (nodeid == 0)
|
||||
return !is_cpu_pre_e0();
|
||||
|
||||
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54 always 0
|
||||
// d0 will be treated as e0 with this methods, but the d0 nb_cfg_54
|
||||
// always 0
|
||||
pci_devfn_t dev;
|
||||
dev = PCI_DEV(0, 0x18+nodeid, 2);
|
||||
val_old = pci_read_config32(dev, 0x80);
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Advanced Micro Devices, Inc.
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
|
||||
* Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -53,7 +53,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr_amd(unsigned int index)
|
|||
return result;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index, msr_t msr)
|
||||
static inline __attribute__((always_inline)) void wrmsr_amd(unsigned int index,
|
||||
msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
|
|
|
|||
|
|
@ -2,7 +2,8 @@
|
|||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 Rudolf Marek <r.marek@assembler.cz>
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
|
||||
* Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>,
|
||||
* Raptor Engineering
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
|
|
|
|||
|
|
@ -83,10 +83,12 @@
|
|||
#define L2CMD_MESI_I 0
|
||||
|
||||
extern int calculate_l2_latency(void);
|
||||
extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way, u8 command);
|
||||
extern int signal_l2(u32 address_low, u32 data_high, u32 data_low, int way,
|
||||
u8 command);
|
||||
extern int read_l2(u32 address);
|
||||
extern int write_l2(u32 address, u32 data);
|
||||
extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high, u32 data_low);
|
||||
extern int test_l2_address_alias(u32 address1, u32 address2, u32 data_high,
|
||||
u32 data_low);
|
||||
extern int calculate_l2_cache_size(void);
|
||||
extern int calculate_l2_physical_address_range(void);
|
||||
extern int set_l2_ecc(void);
|
||||
|
|
|
|||
|
|
@ -13,12 +13,14 @@
|
|||
# define NEED_LAPIC 0
|
||||
#endif
|
||||
|
||||
static inline __attribute__((always_inline)) unsigned long lapic_read(unsigned long reg)
|
||||
static inline __attribute__((always_inline)) unsigned long lapic_read(
|
||||
unsigned long reg)
|
||||
{
|
||||
return *((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg));
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void lapic_write(unsigned long reg, unsigned long v)
|
||||
static inline __attribute__((always_inline)) void lapic_write(unsigned long reg,
|
||||
unsigned long v)
|
||||
{
|
||||
*((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg)) = v;
|
||||
}
|
||||
|
|
@ -67,7 +69,8 @@ void stop_this_cpu(void);
|
|||
|
||||
#if !defined(__PRE_RAM__)
|
||||
|
||||
#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), sizeof(*(ptr))))
|
||||
#define xchg(ptr, v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
|
||||
sizeof(*(ptr))))
|
||||
|
||||
struct __xchg_dummy { unsigned long a[100]; };
|
||||
#define __xg(x) ((struct __xchg_dummy *)(x))
|
||||
|
|
@ -77,7 +80,8 @@ struct __xchg_dummy { unsigned long a[100]; };
|
|||
* Note 2: xchg has side effect, so that attribute volatile is necessary,
|
||||
* but generally the primitive is invalid, *ptr is output argument. --ANK
|
||||
*/
|
||||
static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
|
||||
static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
|
||||
int size)
|
||||
{
|
||||
switch (size) {
|
||||
case 1:
|
||||
|
|
|
|||
|
|
@ -37,7 +37,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
|
|||
return soc_msr_read(index);
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr)
|
||||
static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
|
||||
msr_t msr)
|
||||
{
|
||||
soc_msr_write(index, msr);
|
||||
}
|
||||
|
|
@ -64,7 +65,8 @@ static inline __attribute__((always_inline)) msr_t rdmsr(unsigned int index)
|
|||
return result;
|
||||
}
|
||||
|
||||
static inline __attribute__((always_inline)) void wrmsr(unsigned int index, msr_t msr)
|
||||
static inline __attribute__((always_inline)) void wrmsr(unsigned int index,
|
||||
msr_t msr)
|
||||
{
|
||||
__asm__ __volatile__ (
|
||||
"wrmsr"
|
||||
|
|
|
|||
|
|
@ -147,7 +147,8 @@ static inline unsigned int fls(unsigned int x)
|
|||
# define CACHE_ROM_SIZE CONFIG_ROM_SIZE
|
||||
# else
|
||||
# define CACHE_ROM_SIZE _ALIGN_UP_POW2(CONFIG_ROM_SIZE)
|
||||
# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= (2 * CONFIG_ROM_SIZE))
|
||||
# if (CACHE_ROM_SIZE < CONFIG_ROM_SIZE) || (CACHE_ROM_SIZE >= \
|
||||
(2 * CONFIG_ROM_SIZE))
|
||||
# error "CACHE_ROM_SIZE is not optimal."
|
||||
# endif
|
||||
# endif
|
||||
|
|
|
|||
|
|
@ -474,8 +474,10 @@ void northbridge_smi_handler(void);
|
|||
void southbridge_smi_handler(void);
|
||||
#else
|
||||
void cpu_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
|
||||
void northbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
|
||||
void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
|
||||
void northbridge_smi_handler(unsigned int node,
|
||||
smm_state_save_area_t *state_save);
|
||||
void southbridge_smi_handler(unsigned int node,
|
||||
smm_state_save_area_t *state_save);
|
||||
#endif /* CONFIG_SMM_TSEG */
|
||||
void mainboard_smi_gpi(u32 gpi_sts);
|
||||
int mainboard_smi_apmc(u8 data);
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue