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soc/amd/cezanne: add support for the changed AMD FSP API for USB PHY

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The AMD FSP is using a new structure for USB and USB C phy settings.
This patch removes old, unused structures, adds the new one and
enables the devicetree interface for it.

Signed-off-by: Julian Schroeder <julianmarcusschroeder@gmail.com>
Change-Id: I011ca40a334e4fd26778ca7f18b653298b14019b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/54065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
This commit is contained in:
Julian Schroeder 2021-05-11 10:44:13 -05:00 • committed by Felix Held
commit d2f3308ad7
4 changed files with 72 additions and 21 deletions
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4
src/soc/amd/cezanne/chip.h
View file

@ -8,6 +8,7 @@
#include <soc/southbridge.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <types.h>
#include <vendorcode/amd/fsp/cezanne/FspUsb.h>
struct soc_amd_cezanne_config {
struct soc_amd_common_config common_config;
@ -92,6 +93,9 @@ struct soc_amd_cezanne_config {
GPP_CLK_REQ, /* GPP clock controlled by corresponding #CLK_REQx pin */
GPP_CLK_OFF, /* GPP clk off */
} gpp_clk_config[GPP_CLK_OUTPUT_COUNT];
uint8_t usb_phy_custom;
struct usb_phy_config usb_phy;
};
#endif /* CEZANNE_CHIP_H */

5
src/soc/amd/cezanne/fsp_m_params.c
View file

@ -161,6 +161,11 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
mcfg->enable_nb_azalia = devtree_gfx_hda_dev_enabled();
if (config->usb_phy_custom)
mcfg->usb_phy = (struct usb_phy_config *)&config->usb_phy;
else
mcfg->usb_phy = NULL;
fsp_fill_pcie_ddi_descriptors(mcfg);
fsp_assign_ioapic_upds(mcfg);
}