From d29c78450468fce1d65d00a024551a9d6810c4d9 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Fri, 12 May 2017 17:10:58 +0200 Subject: [PATCH] UPSTREAM: nb/intel/x4x: Fix uninitialized variable issue A left-over from 5e3cb72a71 (nb/x4x: Do not enable IGD when not supported). Should fix coverity issue 1375009. Remove a redundant line that uses the variable `gfxsize` out of its scope and move the variable declaration. Make sure the variable is always initialized, drop unneeded error-handling for `get_option()` and sanitize the read value instead. BUG=none BRANCH=none TEST=none Change-Id: If91dd643c754fd049952065dba56bab731b7f449 Signed-off-by: Patrick Georgi Original-Commit-Id: cfd433b96daa2d2f7f4f99fff7608e110b64dca4 Original-Change-Id: Iee2beda30d8c74df0f412622c3ff3357819e386b Original-Signed-off-by: Nico Huber Original-Reviewed-on: https://review.coreboot.org/19680 Original-Reviewed-by: Philippe Mathieu-Daud Original-Tested-by: build bot (Jenkins) Original-Reviewed-by: Arthur Heymans Original-Reviewed-by: Paul Menzel Reviewed-on: https://chromium-review.googlesource.com/506219 Commit-Ready: Patrick Georgi Tested-by: Patrick Georgi Reviewed-by: Patrick Georgi --- src/northbridge/intel/x4x/early_init.c | 13 +++++-------- 1 file changed, 5 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index 66bce7234c..c70e3862c1 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -27,7 +27,6 @@ void x4x_early_init(void) { - u8 gfxsize; const pci_devfn_t d0f0 = PCI_DEV(0, 0, 0); /* Setup MCHBAR. */ @@ -58,19 +57,17 @@ void x4x_early_init(void) if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); - /* Set preallocated IGD size from cmos */ - if (get_option(&gfxsize, "gfx_uma_size") != CB_SUCCESS) { - /* 6 for 64MB, default if not set in cmos */ + /* Set preallocated IGD size from cmos */ + u8 gfxsize = 6; /* 6 for 64MiB, default if not set in cmos */ + get_option(&gfxsize, "gfx_uma_size"); + if (gfxsize > 12) gfxsize = 6; - } - pci_write_config16(d0f0, D0F0_GGC, - 0x0100 | ((gfxsize + 1) << 4)); + pci_write_config16(d0f0, D0F0_GGC, 0x0100 | (gfxsize + 1) << 4); } else { /* Does not feature internal graphics */ pci_write_config32(d0f0, D0F0_DEVEN, D0EN | D1EN | PEG1EN); pci_write_config16(d0f0, D0F0_GGC, (1 << 1)); } - pci_write_config16(d0f0, D0F0_GGC, 0x0100 | ((gfxsize + 1) << 4)); } static void init_egress(void)