From d281a3c559e7a0d58d07d2e47ed460576bb92387 Mon Sep 17 00:00:00 2001 From: Kun Liu Date: Tue, 20 May 2025 15:52:05 +0800 Subject: [PATCH] mb/google/trulo/var/pujjocento: Configure tcss_aux_ori Resolve the issue that DP can only display on one side. BUG=b:416842915 BRANCH=none TEST=Build and boot to pujjocento. Verify typec works. Change-Id: I55f2f28a0bdb052cafa05a98f51c8483fb343b8c Signed-off-by: Kun Liu Reviewed-on: https://review.coreboot.org/c/coreboot/+/87757 Reviewed-by: Derek Huang Tested-by: build bot (Jenkins) --- .../google/brya/variants/pujjocento/overridetree.cb | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb index 4a9ae54d8a..991fdf054e 100644 --- a/src/mainboard/google/brya/variants/pujjocento/overridetree.cb +++ b/src/mainboard/google/brya/variants/pujjocento/overridetree.cb @@ -49,6 +49,16 @@ chip soc/intel/alderlake register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3 WWAN(LTE) register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC_SKIP)" + + # SOC Aux orientation override: + # This is a bitfield that corresponds to up to 4 TCSS ports. + # Bits (0,1) allocated for TCSS Port1 configuration and Bits (2,3)for TCSS Port2. + # TcssAuxOri = 0101b + # Bit0,Bit2 set to "1" indicates no retimer on USBC Ports + # Bit1,Bit3 set to "0" indicates Aux lines are not swapped on the + # motherboard to USBC connector + register "tcss_aux_ori" = "0" # HD Audio