From d277b353072bb71ad83103dc96cd58a7bbe39d67 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 18 Nov 2025 17:06:49 +0000 Subject: [PATCH] soc/qualcomm/x1p42100: Relocate ddr_information and watchdog tombstone This commit relocates the following two regions: 1. `ddr_information` 2. `WATCHDOG_TOMBSTONE` Previously, these regions were allocated in a higher address range (starting near 0x14800000). The regions are now defined within SSRAM`: - `ddr_information` is moved from `0x14860000` to `0x146ABFE8`. - `WATCHDOG_TOMBSTONE` is moved from `0x14818FFC` to `0x146ABFFC`. This memory map change updates the linker script's visual diagram and section definitions to reflect the new memory layout. BUG=b:456953373 TEST=Able to build google/quenbi. Change-Id: I4545722a836ec472e8086d1a941515cb3956c763 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/90052 Reviewed-by: Kapil Porwal Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/soc/qualcomm/x1p42100/memlayout.ld | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/soc/qualcomm/x1p42100/memlayout.ld b/src/soc/qualcomm/x1p42100/memlayout.ld index 092bac0c9e..5bf877e616 100644 --- a/src/soc/qualcomm/x1p42100/memlayout.ld +++ b/src/soc/qualcomm/x1p42100/memlayout.ld @@ -120,8 +120,6 @@ * | ... Usable memory ... | | * 0x14860C00 +----------------------------------------------------------+ | * | FMAP_CACHE | | - * 0x14860400 +----------------------------------------------------------+ | - * | ddr_information | | * 0x14860000 +----------------------------------------------------------+ BSRAM * | CBFS_MCACHE | | * 0x1485C000 +----------------------------------------------------------+ | @@ -141,16 +139,18 @@ * 0x14828000 +----------------------------------------------------------+ | * | BOOTBLOCK | | * 0x14819000 +----------------------------------------------------------+ | - * | WATCHDOG_TOMBSTONE | | - * 0x14818FFC +----------------------------------------------------------+ | * | ... Usable memory ... | | * 0x14815000 +----------------------------------------------------------+ | * | pbl_timestamps | v * 0x14800000 +----------------------------------------------------------+ <--------- * | ... (Large Address Gap) ... | + * +----------------------------------------------------------+ + * | ... Usable memory ... | * 0x146AC000 +----------------------------------------------------------+ <--------- - * | ... Usable memory ... | ^ - * 0x146AB000 +----------------------------------------------------------+ | + * | WATCHDOG_TOMBSTONE | ^ + * 0x146ABFFC +----------------------------------------------------------+ | + * | ddr_information | | + * 0x146ABFE8 +----------------------------------------------------------+ | * | shared_imem | | * 0x146AA000 +----------------------------------------------------------+ | * | ... Usable memory ... | SSRAM @@ -183,11 +183,12 @@ SECTIONS STACK(0x14680000, 16K) REGION(qcsdi, 0x14699000, 48K, 4K) REGION(shared_imem, 0x146AA000, 0x1000, 4K) + REGION(ddr_information, 0x146ABFE8, 16, 8) + WATCHDOG_TOMBSTONE(0x146ABFFC, 4) SSRAM_END(0x146AC000) BSRAM_START(0x14800000) REGION(pbl_timestamps, 0x14800000, 84K, 4K) - WATCHDOG_TOMBSTONE(0x14818FFC, 4) BOOTBLOCK(0x14819000, 60K) PRERAM_CBFS_CACHE(0x14828000, 103K) TIMESTAMP(0x14841C00, 1K) @@ -196,7 +197,6 @@ SECTIONS DMA_COHERENT(0x14857000, 8K) REGION(qclib_serial_log, 0x1485B000, 4K, 4K) CBFS_MCACHE(0x1485C000,16K) - REGION(ddr_information, 0x14860000, 1K, 1K) FMAP_CACHE(0x14860400, 2K) REGION(dcb, 0x14862000, 56K, 4K) REGION(dtb, 0x14870000, 32K, 4K)