src/soc/mt8196: Correct systimer register offset
A recent datasheet review finds that the previously used offset for the `cnttval` register is incorrect. Since the relevant bits used by `clear_timer()` have default values of 0, the functionality is not affected before this fix. BUG=b:430211678 BRANCH=rauru TEST=check the timestamp order of depthcharge is correct in `cbmem` 16:finished LZMA decompress (ignore for x86) 895,082 (526) 1000:depthcharge start 941,621 (46,539) 1002:RO vboot init 942,644 (1,023) 1020:vboot select&load kernel 942,645 (1) 1030:finished EC verification 980,005 (37,360) 1060:finished AuxFW Sync 997,302 (17,297) 1040:finished storage device initialization 1,025,910 (28,608) 1050:finished reading kernel from disk 2,174,931 (1,149,021) 1100:finished vboot kernel verification 2,229,874 (54,943) 1102:starting kernel decompression/relocation 2,249,121 (19,247) 1101:jumping to kernel 2,284,317 (35,196) Total Time: 2,020,762 Change-Id: I018d81de79d6896a31972f925d5a26f41cf942a0 Signed-off-by: Vince Liu <vince-wl.liu@mediatek.corp-partner.google.com> Signed-off-by: Zhanzhan Ge <zhanzhan.ge@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/88480 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1 changed files with 4 additions and 2 deletions
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@ -31,7 +31,7 @@ struct systimer {
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u32 reserved;
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u32 cntcv_l;
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u32 cntcv_h;
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u32 reserved1[0x30];
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u32 reserved1[12];
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struct {
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u32 con;
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u32 val;
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@ -40,6 +40,8 @@ struct systimer {
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check_member(systimer, cntcr, 0x0);
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check_member(systimer, cntcv_l, 0x0008);
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check_member(systimer, cntcv_h, 0x000c);
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check_member(systimer, cntcv_h, 0x000C);
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check_member(systimer, cnttval[0].con, 0x0040);
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check_member(systimer, cnttval[0].val, 0x0044);
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#endif
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