From d19cb011294d33cf06d5fe508ff186d0dee97af0 Mon Sep 17 00:00:00 2001 From: Ren Kuo Date: Wed, 21 Jan 2026 14:46:37 +0800 Subject: [PATCH] mb/google/fatcat/moonstone: Remove RTD3 config for SSD The Moonstone hardware design does not have a power load switch for the SSD. Without it, the platform cannot cut off the main power rail to the device to enter D3cold. Therefore, remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree to align with the hardware capability. The system will support D3hot instead of D3cold. BUG=460038237 TEST=Build and boot to OS on Moonstone, verify SSD still functions correctly and power state transitions align with HW design. Change-Id: I8fd12d2f629977f939d11f26aef21552a947c5e3 Signed-off-by: Ren Kuo Reviewed-on: https://review.coreboot.org/c/coreboot/+/90841 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Pranava Y N --- .../google/fatcat/variants/moonstone/overridetree.cb | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb index 17d461248c..16847cc41f 100644 --- a/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/moonstone/overridetree.cb @@ -390,13 +390,6 @@ chip soc/intel/pantherlake .clk_req = 1, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "is_storage" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B16)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E03)" - register "srcclk_pin" = "1" - device generic 0 on end - end end # Gen5 M.2 SSD device ref cnvi_wifi on chip drivers/wifi/generic