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UPSTREAM: soc/intel/skylake: Add entry for deep Sx wake

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If deep Sx is enabled and prev sleep state was not S0, then if SUS
power was lost, it means that the platform had entered deep Sx. Add an
elog entry for deep Sx variant in this case.

BUG=b:38436041
TEST=Verified that elog entries are updated correctly:

Deep S5:
59 | 2017-05-19 10:39:08 | Kernel Event | Clean Shutdown
60 | 2017-05-19 10:39:09 | ACPI Enter | S5
61 | 2017-05-19 10:39:17 | System boot | 22
62 | 2017-05-19 10:39:17 | EC Event | Power Button
63 | 2017-05-19 10:39:17 | ACPI Deep Sx Wake | S5
64 | 2017-05-19 10:39:17 | Wake Source | Power Button | 0
65 | 2017-05-19 10:39:17 | Chrome OS Developer Mode

Deep S3:
66 | 2017-05-19 10:40:11 | ACPI Enter | S3
67 | 2017-05-19 10:40:16 | EC Event | Power Button
68 | 2017-05-19 10:40:16 | ACPI Deep Sx Wake | S3
69 | 2017-05-19 10:40:16 | Wake Source | Power Button | 0

Normal S3:
77 | 2017-05-19 10:43:22 | ACPI Enter | S3
78 | 2017-05-19 10:43:39 | EC Event | Power Button
79 | 2017-05-19 10:43:39 | ACPI Wake | S3
80 | 2017-05-19 10:43:39 | Wake Source | Power Button | 0

Change-Id: Ic052854ef87fc88d4c25b6d14b8deb4fafe1f0fc
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 7941c96f8e
Original-Change-Id: Ia251334ae44668c2260d8d2e816f85f1f62faac4
Original-Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19798
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/513951
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Furquan Shaikh 2017-05-19 10:54:30 -07:00 • committed by chrome-bot
commit d1463b0304
1 changed files with 20 additions and 4 deletions
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24
src/soc/intel/skylake/elog.c
View file

@ -70,6 +70,17 @@ static void pch_log_wake_source(struct chipset_power_state *ps)
static void pch_log_power_and_resets(struct chipset_power_state *ps)
{
bool deep_sx;
/*
* Platform entered deep Sx if:
* 1. Prev sleep state was Sx and deep_sx_enabled() is true
* 2. SUS well power was lost
*/
deep_sx = ((((ps->prev_sleep_state == ACPI_S3) && deep_s3_enabled()) ||
((ps->prev_sleep_state == ACPI_S5) && deep_s5_enabled())) &&
(ps->gen_pmcon_b & SUS_PWR_FLR));
/* Thermal Trip */
if (ps->gblrst_cause[0] & GBLRST_CAUSE0_THERMTRIP)
elog_add_event(ELOG_TYPE_THERM_TRIP);
@ -81,8 +92,7 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
/* SUS Well Power Failure */
if (ps->gen_pmcon_b & SUS_PWR_FLR) {
/* Do not log SUS_PWR_FLR if waking from deep Sx */
if (!(ps->prev_sleep_state == ACPI_S3 && deep_s3_enabled()) &&
!(ps->prev_sleep_state == ACPI_S5 && deep_s5_enabled()))
if (!deep_sx)
elog_add_event(ELOG_TYPE_SUS_POWER_FAIL);
}
@ -104,8 +114,14 @@ static void pch_log_power_and_resets(struct chipset_power_state *ps)
elog_add_event(ELOG_TYPE_SYSTEM_RESET);
/* ACPI Wake Event */
if (ps->prev_sleep_state != ACPI_S0)
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE, ps->prev_sleep_state);
if (ps->prev_sleep_state != ACPI_S0) {
if (deep_sx)
elog_add_event_byte(ELOG_TYPE_ACPI_DEEP_WAKE,
ps->prev_sleep_state);
else
elog_add_event_byte(ELOG_TYPE_ACPI_WAKE,
ps->prev_sleep_state);
}
}
static void pch_log_state(void *unused)