erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

arm: libpayload: Add cache coherent DMA memory definition and management

Browse source 
This patch adds a mechanism to set aside a region of cache-coherent
(i.e. usually uncached) virtual memory, which can be used to communicate
with DMA devices without automatic cache snooping (common on ARM)
without the need of explicit flush/invalidation instructions in the
driver code.

This works by setting aside said region in the (board-specific) page
table setup, as exemplary done in this patch for the Snow, Pit and Kirby
boards. It uses a new mechanism for adding board-specific Coreboot table
entries to describe this region in an entry with the LB_DMA tag.

Libpayload's memory allocator is enhanced to be able to operate on
distinct types/regions of memory. It provides dma_malloc() and
dma_memalign() functions for use in drivers, which by default just
operate on the same heap as their traditional counterparts. However, if
the Coreboot table parsing code finds a CB_DMA section, further requests
through the dma_xxx() functions will return memory from the region
described therein instead.

BUG=chrome-os-partner:21969
TEST=Manual

Change-Id: Ia9c249249e936bbc3eb76e7b4822af2230ffb186
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/167155
This commit is contained in:
Julius Werner 2013-08-27 15:48:32 -07:00 • committed by Caroline Tice
commit d142ccdcd9
9 changed files with 158 additions and 42 deletions
Download patch file Download diff file Expand all files Collapse all files

6
src/include/boot/coreboot_tables.h
View file

@ -216,6 +216,7 @@ struct lb_gpios {
#define LB_TAG_VDAT 0x0015
#define LB_TAG_VBNV 0x0019
#define LB_TAB_VBOOT_HANDOFF 0x0020
#define LB_TAB_DMA 0x0022
struct lb_range {
uint32_t tag;
uint32_t size;
@ -331,4 +332,9 @@ struct lb_memory *get_lb_mem(void);
void fill_lb_gpios(struct lb_gpios *gpios);
/* Define this in mainboard.c to add board-specific table entries. */
void lb_board(struct lb_header *header);
struct lb_record *lb_new_record(struct lb_header *header);
#endif /* COREBOOT_TABLES_H */

7
src/lib/coreboot_table.c
View file

@ -79,7 +79,7 @@ static struct lb_record *lb_last_record(struct lb_header *header)
return rec;
}
static struct lb_record *lb_new_record(struct lb_header *header)
struct lb_record *lb_new_record(struct lb_header *header)
{
struct lb_record *rec;
rec = lb_last_record(header);
@ -364,6 +364,8 @@ static void lb_strings(struct lb_header *header)
}
void __attribute__((weak)) lb_board(struct lb_header *header) { /* NOOP */ }
static struct lb_forward *lb_forward(struct lb_header *header, struct lb_header *next_header)
{
struct lb_record *rec;
@ -576,6 +578,9 @@ unsigned long write_coreboot_table(
#endif
add_cbmem_pointers(head);
/* Add board-specific table entries, if any. */
lb_board(head);
/* Remember where my valid memory ranges are */
return lb_table_fini(head);
}

16
src/mainboard/google/kirby/mainboard.c
View file

@ -45,6 +45,10 @@
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -441,6 +445,7 @@ static void mainboard_enable(device_t dev)
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
tlb_invalidate_all();
/* this is going to move, but we must have it now and we're
@ -459,3 +464,14 @@ struct chip_operations mainboard_ops = {
.name = "Google ARM Chromebook",
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
}

16
src/mainboard/google/pit/mainboard.c
View file

@ -45,6 +45,10 @@
#define DRAM_START (CONFIG_SYS_SDRAM_BASE >> 20)
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -462,6 +466,7 @@ static void mainboard_enable(device_t dev)
/* set up caching for the DRAM */
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
tlb_invalidate_all();
/* this is going to move, but we must have it now and we're
@ -482,3 +487,14 @@ struct chip_operations mainboard_ops = {
.name = "Samsung/Google ARM Chromebook",
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
}

16
src/mainboard/google/snow/mainboard.c
View file

@ -46,6 +46,10 @@
#define DRAM_SIZE CONFIG_DRAM_SIZE_MB
#define DRAM_END (DRAM_START + DRAM_SIZE) /* plus one... */
/* Arbitrary range of DMA memory for depthcharge's drivers */
#define DMA_START (0x77300000)
#define DMA_SIZE (0x00100000)
static struct edid edid = {
.ha = 1366,
.va = 768,
@ -330,6 +334,7 @@ static void mainboard_enable(device_t dev)
mmu_init();
mmu_config_range(0, DRAM_START, DCACHE_OFF);
mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK);
mmu_config_range(DMA_START >> 20, DMA_SIZE >> 20, DCACHE_OFF);
mmu_config_range(DRAM_END, 4096 - DRAM_END, DCACHE_OFF);
dcache_invalidate_all();
dcache_mmu_enable();
@ -352,3 +357,14 @@ struct chip_operations mainboard_ops = {
.name = "Samsung/Google ARM Chromebook",
.enable_dev = mainboard_enable,
};
void lb_board(struct lb_header *header)
{
struct lb_range *dma;
dma = (struct lb_range *)lb_new_record(header);
dma->tag = LB_TAB_DMA;
dma->size = sizeof(*dma);
dma->range_start = (intptr_t)DMA_START;
dma->range_size = DMA_SIZE;
}