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mb/google/brox/var/lotso: disable RTS5227 PCIE L0s support

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Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1.

lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled.

BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage

Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
This commit is contained in:
Jian Tong 2024-09-02 14:26:00 +08:00 • committed by Felix Held
commit d1243fcaad
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/brox/variants/lotso/overridetree.cb
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@ -357,6 +357,7 @@ chip soc/intel/alderlake
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
.pcie_rp_aspm = ASPM_L1,
}"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)"