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armv7: Support stack dump after exceptions

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This patch enhances the armv7 exception handlers in Coreboot and
libpayload to show the correct SP and LR registers from the aborted
context, and also dump a part of the current stack. Since we cannot
access the banked registers of SVC mode from a different exception mode,
it changes Coreboot (and its payloads) to run in System mode instead. As
both modes can execute all privileged instructions, this should not have
any noticeable effect on firmware operation (please correct me if I'm
wrong!).

BUG=None
TEST=Cause a data_abort in Coreboot or depthcharge. Marvel at the
beautifully displayed stack dump that helps you debug the abort.

Change-Id: I0e04f47619e55308f7da4a3a99c9cae6ae35cc30
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/170045
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
This commit is contained in:
Julius Werner 2013-09-18 14:39:50 -07:00 • committed by chrome-internal-fetch
commit d0db2f5e93
7 changed files with 67 additions and 29 deletions
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4
src/cpu/samsung/exynos5420/smp.c
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@ -168,7 +168,7 @@ static void core_start_execution(void)
u32 cpu_id, cpu_state;
enable_smp();
set_svc32_mode();
set_system_mode();
cpu_id = read_mpidr() & 0x3; /* up to 4 processors for one cluster. */
cpu_state = exynos_cpu_states->cpu_states[cpu_id];
@ -220,7 +220,7 @@ static void low_power_start(void)
sev();
}
set_svc32_mode();
set_system_mode();
/* Whenever a Cortex A-15 core powers on, iROM resets its L2 cache
* so we need to configure again. */