diff --git a/src/mainboard/gigabit/ga-6bxc/mtrr_table.c b/src/mainboard/gigabit/ga-6bxc/mtrr_table.c
new file mode 100644
index 0000000000..a99b336b5b
--- /dev/null
+++ b/src/mainboard/gigabit/ga-6bxc/mtrr_table.c
@@ -0,0 +1,47 @@
+#include <cpu/p6/mtrr.h>
+
+unsigned char fixed_mtrr_values[][4] = {
+	/* MTRRfix64K_00000_MSR, defines memory range from 0KB to 512 KB, each byte cover 64KB area */
+	{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
+	{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
+
+	/* MTRRfix16K_80000_MSR, defines memory range from 512KB to 640KB, each byte cover 16KB area */
+	{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
+	{MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK, MTRR_TYPE_WRBACK},
+
+	/* MTRRfix16K_A0000_MSR, defines memory range from A0000 to C0000, each byte cover 16KB area */
+	{MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB},
+	{MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB, MTRR_TYPE_WRCOMB},
+
+	/* MTRRfix4K_C0000_MSR, defines memory range from C0000 to C8000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+
+	/* MTRRfix4K_C8000_MSR, defines memory range from C8000 to D0000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+
+	/* MTRRfix4K_D0000_MSR, defines memory range from D0000 to D8000, each byte cover 4KB area */
+	{MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE},
+	{MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE, MTRR_TYPE_UNCACHABLE},
+
+	/* MTRRfix4K_D8000_MSR, defines memory range from D8000 to E0000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+
+	/* MTRRfix4K_E0000_MSR, defines memory range from E0000 to E8000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+
+	/* MTRRfix4K_E8000_MSR, defines memory range from E8000 to F0000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+
+	/* MTRRfix4K_F0000_MSR, defines memory range from F0000 to F8000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+
+	/* MTRRfix4K_F8000_MSR, defines memory range from F8000 to 100000, each byte cover 4KB area */
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+	{MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH, MTRR_TYPE_WRTHROUGH},
+};
diff --git a/src/pcibridge/TI/pci1225/Config b/src/pcibridge/TI/pci1225/Config
new file mode 100644
index 0000000000..d593cd9329
--- /dev/null
+++ b/src/pcibridge/TI/pci1225/Config
@@ -0,0 +1 @@
+object ti-pci1225.o
diff --git a/src/pcibridge/TI/pci1225/ti-pci1225.c b/src/pcibridge/TI/pci1225/ti-pci1225.c
new file mode 100644
index 0000000000..e0c399a018
--- /dev/null
+++ b/src/pcibridge/TI/pci1225/ti-pci1225.c
@@ -0,0 +1,86 @@
+
+/*
+ * This code is totally non-portable to any system that doesn't
+ * happen to match the one it was written for.  This really needs
+ * to be done as a set of utilities that mainboard_fixup() can call
+ * as needed and with the right arguements for the configuration
+ * of the board.
+ */
+
+#include <subr.h>
+#include <pci.h>
+#include <pci_ids.h>
+
+int ti_pci1225_setup() {
+
+  struct pci_dev *pcidev;
+  struct pci_dev *pcidev1;
+  struct pci_dev *pcidev2;
+
+  int slot;
+  int func;
+  int bus;
+  
+  /*
+   * setup serial interrupt in the PIIX4.
+   *
+   * This code has no business being here.  There should be
+   * utility functions in southbridge.c that mainboard_fixup()
+   * calls to do this before trying to enable pci1225 chip.
+   */
+
+  pcidev = pci_find_device(PCI_VENDOR_INTEL,
+			   PCI_DEVICE_ID_INTEL_82371AB_0,
+			   (void *)NULL);
+
+  if (!pcidev) return(-1);
+
+  pci_write_config_byte(pcidev, 0x64, 0xd0);
+  pci_write_config_byte(pcidev, 0xb2, 0x01);
+
+
+  /*
+   * Setup the TI PCI1225 registers to match the PnR
+   *
+   * At least this code belongs in this file.  However
+   * it needs to be provided as utility functions that 
+   * mainboard_fixup() can use to fixup the main board.
+   */
+
+  pcidev = pci_find_device(PCI_VENDOR_TI,
+			   PCI_DEVICE_TI_1225,
+			   (void *)NULL);
+
+  if (!pcidev) return(-2);
+
+  pcidev2 = pci_find_device(PCI_VENDOR_TI,
+			   PCI_DEVICE_TI_1225,
+			   pcidev);
+
+  if (!pcidev2) return(-3);
+
+  if ((pcidev2->vendor != pcidev->vendor) ||
+      (pcidev2->device != pcidev->device) ||
+      (pcidev2->class  != pcidev->class )) return (-4);
+
+  /* Are we guarenteed to get chip functions in order? */
+
+  if (pcidev->devfn < pcidev2->devfn) {
+    pcidev1 = pcidev;
+  }
+  else {
+    pcidev1 = pcidev2;
+    pcidev2 = pcidev;
+  }
+
+  pci_write_config_byte (pcidev1, 0x3c,       0xff);
+  pci_write_config_byte (pcidev2, 0x3c,       0xff);
+
+  pci_write_config_dword(pcidev1, 0x80, 0x2844b060);
+  pci_write_config_dword(pcidev1, 0x8c, 0x00001002);
+  pci_write_config_byte (pcidev1, 0x90,       0xc0);
+  pci_write_config_byte (pcidev1, 0x91,       0x02);
+  pci_write_config_byte (pcidev1, 0x92,       0x64);
+
+  return(0);
+}
diff --git a/src/superio/SMC/fdc37n769/setup_serial.inc b/src/superio/SMC/fdc37n769/setup_serial.inc
new file mode 100644
index 0000000000..b2c82a5753
--- /dev/null
+++ b/src/superio/SMC/fdc37n769/setup_serial.inc
@@ -0,0 +1,94 @@
+/*
+ * Enable the peripheral devices on the FDC37N769 Super IO chip
+ */
+
+/*
+ * This code is untested but should at least get a serial port working.
+ *   -Tyson
+ */
+
+/* The base address is either 0x3F0 or 0x370, depending on config pin */
+
+#ifndef SMC_BASE
+#error SMC_BASE must be defined as 0x3F0 or 0x370
+#endif
+
+#if (SMC_BASE == 0x370)
+/* #warning SMC_BASE set to 0x370 */
+#elif (SMC_BASE == 0x3f0)
+/* #warning SMC_BASE set to 0x3f0 */
+#else
+#error SMC_BASE defined as other than 0x3F0 or 0x370
+#endif
+
+#define SMC_INDEX SMC_BASE
+#define SMC_DATA  SMC_BASE+1
+
+#define SMC_READ(index) \
+	mov index, %al		; \
+	mov $SMC_BASE, %dx	; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	inb %dx, %al		;
+
+#define SMC_WRITE(data, index) \
+	mov data, %ah		; \
+	mov index, %al		; \
+	mov $SMC_BASE, %dx	; \
+	outb %al, %dx		; \
+	inc %dx			; \
+	mov %ah, %al		; \
+	outb %al, %dx		;
+
+	
+	/* Enter the configuration state */
+
+	mov $0x55, %al
+	mov $SMC_BASE, %dx
+	outb %al, %dx
+
+	/* Check for Device ID */
+
+	SMC_READ($0x0d)
+	cmp %al, 0x28
+	je 2f
+	mov $0xfe, %al
+	outb %al, $0x80
+#if 0
+1:	hlt
+	jmp	1b
+#endif
+2:
+
+	/* Pin configuration - need to enable IRQ 4 output */
+	
+	SMC_WRITE($0xf4, $0x03)	;
+
+	/* Set address of parallel port */
+#if 0
+	SMC_WRITE($0xde, $0x23)	;
+#endif
+	/* Set address of serial port 0 */
+
+	SMC_WRITE($0xfe, $0x24)	;
+
+	/* Set address of serial port 1 */
+
+	SMC_WRITE($0xbe, $0x25)	;
+
+	/* Set IRQs of serial ports */
+
+	SMC_WRITE($0x21, $0x28)	;
+
+	/* Set valid bit */
+
+	SMC_READ($0x00)
+	or $0x80, %al
+	SMC_WRITE(%al, $0x00)
+	
+	/* Exit the configuration state */
+
+	mov $0xAA, %al
+	mov $SMC_BASE, %dx
+	outb %al, %dx
+
diff --git a/src/superio/SMC/fdc37n769/superio.c b/src/superio/SMC/fdc37n769/superio.c
new file mode 100644
index 0000000000..aab3f6a477
--- /dev/null
+++ b/src/superio/SMC/fdc37n769/superio.c
@@ -0,0 +1,213 @@
+#include <subr.h>
+#include <cpu/p5/io.h>
+
+/*
+ * This file is for setting up the SMC Super IO chip.  
+ *
+ * This file contains some hard coded mappings for IRQs which may
+ * work for most boards but is really board specific.  A
+ * configuration mechanism is needed.
+ *
+ * I have only implemented the UART features that I needed at
+ * the time plus enableing EPP mode to get interrupts that can
+ * be shared.  Other features for floppies and parallel ports
+ * can be added by others as needed.
+ *
+ *  -Tyson Sawyer  tyson@rwii.com
+ *
+ * Sharing interrupts between two SMC chips doesn't work for me. -tds
+ */
+
+static int smc_configuration_state(int addr, int state) {
+
+  if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
+
+  if (state) {
+    outb(0x55, addr);
+    return(0);
+  }
+  else {
+    outb(0xAA, addr);
+    return(0);
+  }
+ 
+  return(-1);
+}
+
+static int smc_write(int addr, unsigned char data, unsigned char index) {
+
+  if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
+
+  outb(index, addr);
+  outb(data, addr+1);
+  return(0);
+}
+
+static int smc_read(int addr, unsigned char index, unsigned char *data) {
+
+  if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
+
+  outb(index, addr);
+  *data = inb(addr+1);
+  return(0);
+}
+
+int smc_uart_setup(int addr,
+		   int addr1, int irq1,
+		   int addr2, int irq2) {
+
+  int rv;
+  unsigned char int1, int2;
+  unsigned char data;
+
+  if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
+
+  /*
+   * Warning:
+   * Board specifc mapping of IRQs here.
+   * A configuration mechanism is needed.
+   */
+
+  switch (irq1) {
+  case  3: int1 = 1; break;
+  case  4: int1 = 2; break;
+  case  5: int1 = 3; break;
+  case  6: int1 = 4; break;
+  case  7: int1 = 5; break;
+  case 10: int1 = 6; break;
+  case 11: int1 = 8; break;
+  default: int1 = 0;
+  }
+
+  switch (irq2) {
+  case  3: int2 = 1; break;
+  case  4: int2 = 2; break;
+  case  5: int2 = 3; break;
+  case  6: int2 = 4; break;
+  case  7: int2 = 5; break;
+  case 10: int2 = 6; break;
+  case 11: int2 = 8; break;
+  default: int2 = 0;
+  }
+
+  if (int1 == int2) {
+    int2 = 0x0f;
+  }
+
+  rv = smc_configuration_state(addr, 1); if (rv) return(rv);
+  rv = smc_write(addr, (addr1>>2) & 0xfe, 0x24); if (rv) return(rv);
+  rv = smc_write(addr, (addr2>>2) & 0xfe, 0x25); if (rv) return(rv);
+  rv = smc_write(addr, (int1<<4) | int2, 0x28); if (rv) return(rv);
+
+  /* Enable INTB output */
+
+  if ((int1==2) || (int2==2)) {
+    rv = smc_read(addr, 0x03, &data); if (rv) return(rv);
+    rv = smc_write(addr, data | 0x84, 0x03);  if (rv) return(rv);
+  }
+
+  rv = smc_configuration_state(addr, 0); return(rv);
+}
+
+int smc_pp_setup(int addr, int pp_addr, int mode) {
+  int rv;
+  unsigned char data;
+
+  rv = smc_configuration_state(addr, 1); if (rv) return(rv);
+
+  rv = smc_read(addr, 0x04, &data); if (rv) return(rv);
+  data = (data & (~0x03)) | (mode & 0x03);
+  rv = smc_write(addr, data, 0x04);  if (rv) return(rv);
+
+  rv = smc_read(addr, 0x01, &data); if (rv) return(rv);
+  data = data & (~0x08);
+  rv = smc_write(addr, data, 0x01);  if (rv) return(rv);
+
+  rv = smc_write(addr, (pp_addr>>2) & 0xff, 0x23);  if (rv) return(rv);
+
+  rv = smc_configuration_state(addr, 0); return(rv);
+}
+
+int smc_validbit(int addr, int valid) {
+  int rv;
+  unsigned char data;
+
+  if ((addr!=0x370) && (addr!=0x3f0)) return(-1);
+
+  rv = smc_configuration_state(addr, 1); if (rv) return(rv);
+  rv = smc_read(addr, 0x00, &data); if (rv) return(rv);
+
+  if (valid) {
+    data = data | 0x80;
+  }
+  else {
+    data = data & (~0x80);
+  }
+
+  rv = smc_write(addr, data, 0x00);  if (rv) return(rv);
+  rv = smc_configuration_state(addr, 0); return(rv);
+}
+
+/*
+ * ============== Linux bios standard superio functions ========
+ *
+ * These functions suck.
+ */
+
+void
+enter_pnp()
+{
+	// unlock it XXX make this a subr at some point 
+    // outb(0x87, PNPADDR);
+    // outb(0x87, PNPADDR);
+}
+
+void
+exit_pnp()
+{
+	/* all done. */
+	// select configure control
+    // outb(0xaa, PNPADDR);
+}
+
+#ifdef MUST_ENABLE_FLOPPY
+
+void enable_floppy()
+{
+	/* now set the LDN to floppy LDN */
+// 	outb(0x7, PNPADDR);	/* pick reg. 7 */
+// 	outb(0x0, PNPDATA);	/* LDN 0 to reg. 7 */
+
+	/* now select register 0x30, and set bit 1 in that register */
+// 	outb(0x30, PNPADDR);
+// 	outb(0x1, PNPDATA);
+}
+#endif /* MUST_ENABLE_FLOPPY */
+
+void
+enable_com(int com)
+{
+  //   unsigned char b;
+    /* now set the LDN to com LDN */
+    // outb(0x7, PNPADDR);	/* pick reg. 7 */
+    // outb(com, PNPDATA);	/* LDN 0 to reg. 7 */
+
+    /* now select register 0x30, and set bit 1 in that register */
+    // outb(0x30, PNPADDR);
+    // outb(0x1, PNPDATA);
+
+}
+
+void
+final_superio_fixup()
+{
+
+    enter_pnp();
+#ifdef MUST_ENABLE_FLOPPY
+    enable_floppy();
+#endif
+    enable_com(PNP_COM1_DEVICE);
+    enable_com(PNP_COM2_DEVICE);
+
+    exit_pnp();
+}
diff --git a/src/superio/SMC/fdc37n769/superio.h b/src/superio/SMC/fdc37n769/superio.h
new file mode 100644
index 0000000000..a5b680181e
--- /dev/null
+++ b/src/superio/SMC/fdc37n769/superio.h
@@ -0,0 +1,17 @@
+#ifndef _SMC_SUPER_IO_H_
+#define _SMC_SUPER_IO_H_
+
+#define SMC_PP_MODE_SPP     0x00
+#define SMC_PP_MODE_EPP_SPP 0x01
+#define SMC_PP_MODE_ECP     0x02
+#define SMC_PP_MODE_EPP_ECP 0x03
+
+int smc_uart_setup(int smc_addr,
+		   int addr1, int irq1,
+		   int addr2, int irq2);
+
+int smc_pp_setup(int smc_addr, int pp_addr, int mode);
+
+int smc_validbit(int smc_addr, int valid);
+
+#endif /* _SMC_SUPER_IO_H_ */