arch: clean up Kconfig and Makefile

remove some unused code

BRANCH=none
TEST=none
BUG=none
Signed-off-by: Stefan Reinauer <reinauer@google.com>

Change-Id: I048f111b4f4c7a6c987cc7404bd073848619e908
Reviewed-on: https://gerrit.chromium.org/gerrit/57017
Reviewed-by: Ronald G. Minnich <rminnich@chromium.org>
Commit-Queue: Stefan Reinauer <reinauer@google.com>
Tested-by: Stefan Reinauer <reinauer@google.com>

src/arch/armv7/Kconfig

@@ -1,9 +1,5 @@
 menu "Architecture (armv7)"
 
-config EABI_COMPAT
-	bool "Toolchain is EABI compatible"
-	default n
-
 # Maximum reboot count
 # TODO: Improve description.
 config MAX_REBOOT_CNT
@@ -36,17 +32,4 @@ config UPDATE_IMAGE
 	  is a suitable file for further processing.
 	  The bootblock will not be modified.
 
-config BOOTBLOCK_SOC_INIT
-	string
-
-# FIXME: Should cache policy be set on a per-CPU basis?
-# FIXME(dhendrix): Stefan sayz to make a smart decision and not prompt the user.
-config ARM_DCACHE_POLICY_WRITEBACK
-	bool
-	default y
-
-config ARM_DCACHE_POLICY_WRITETHROUGH
-	bool
-	default n
-
 endmenu

src/arch/x86/Kconfig

@@ -94,14 +94,6 @@ config HAVE_ARCH_MEMCPY
 	bool
 	default y
 
-config BIG_ENDIAN
-	bool
-	default n
-
-config LITTLE_ENDIAN
-	bool
-	default !BIG_ENDIAN
-
 config IOAPIC_INTERRUPTS_ON_FSB
 	bool
 	default y if !IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
@@ -110,10 +102,6 @@ config IOAPIC_INTERRUPTS_ON_APIC_SERIAL_BUS
 	bool
 	default n
 
-config PCI_CONF2
-	bool
-	default n
-
 config HPET_ADDRESS
 	hex
 	default 0xfed00000 if !HPET_ADDRESS_OVERRIDE

src/arch/x86/lib/Makefile.inc

@@ -1,7 +1,6 @@
 ramstage-y += c_start.S
 ramstage-y += cpu.c
 ramstage-y += pci_ops_conf1.c
-ramstage-$(CONFIG_PCI_CONF2) += pci_ops_conf2.c
 ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
 ramstage-y += exception.c
 ramstage-$(CONFIG_IOAPIC) += ioapic.c