added spd scan for piix4e
This commit is contained in:
Ronald G. Minnich
parent
b101440e7d
commit
cf7729a729
1 changed files with 298 additions and 0 deletions
298
util/scanspd/spd_piix4e.c
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298
util/scanspd/spd_piix4e.c
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#ifndef __KERNEL__
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#include <stdio.h>
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#endif
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#include <asm/io.h>
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#ifndef __KERNEL__
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typedef unsigned short u16;
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typedef unsigned long u32;
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#define CONFIG_CMD(bus,devfn, where) (0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3))
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static int pci_conf1_write_config_byte(unsigned char bus, int devfn, int where, unsigned char value)
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{
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outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
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outb(value, (0xCFC + (where&2)));
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return 0;
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}
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static int pci_conf1_write_config_word(unsigned char bus, int devfn, int where, u16 value)
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{
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outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
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outw(value, (0xCFC + (where&2)));
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return 0;
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}
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static int pci_conf1_write_config_dword(unsigned char bus, int devfn, int where, u32 value)
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{
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outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
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outl(value, 0xcfc);
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return 0;
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}
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static int pci_conf1_read_config_word(unsigned char bus, int devfn, int where, u16 *value)
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{
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outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
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*value = inw(0xCFC + (where&2));
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return 0;
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}
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static int pci_conf1_read_config_dword(unsigned char bus, int devfn, int where, u32 *value)
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{
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u32 retval;
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int i, j;
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outl(CONFIG_CMD(bus,devfn,where), 0xCF8);
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retval = inl(0xCFC);
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*value = retval;
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return 0;
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}
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#endif
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#include <linux/pci.h>
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/* Define register offsets */
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#define SMBHSTSTS 0x00
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#define SMBHSTCTL 0x02
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#define SMBHSTCMD 0x03 // Register tells what data to get
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#define SMBHSTADD 0x04
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#define SMBHSTDAT0 0x05
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#define SMBHSTDAT1 0x06
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#define SMBBLKDAT 0x07
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/* Define register settings */
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#define HOST_RESET 0x8e
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#define DIMM_BASE 0xa0 // 1010000 is base for DIMM in SMBus
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#define READ_CMD 0x01 // 1 in the 0 bit of SMBHSTADD states to READ
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/* Define SPD Data locations */
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#define MEM_TYPE 2 // Memory Type - EDO, FPM, SDRAM
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#define NUM_ROWS 3 // Number of Row Addresses
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#define NUM_COLS 4 // Number of Column Addresses
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#define NUM_MOD_ROWS 5 // Number of Module Rows
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#define CAS_LAT 18 // CAS Latencies Supported
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#define MOD_ATTR 21 // SDRAM Module Attributes
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#define BANK_DENSITY 31 // Module Bank Density
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#define SPD_REV 62 // SPD Revision
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#define SPEC_FREQ 126 // Specification Frequency - 66, 100, ...
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inline void waitbusy(unsigned short baseaddr);
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inline int waitstatus(unsigned short baseaddr);
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int error_check(unsigned short baseaddr);
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int main()
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{
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int devfn;
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unsigned short baseaddr;
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int dimm;
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int status;
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int data;
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int rows, density; // For RAM size calcs
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u32 val;
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int i;
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iopl(3);
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// Find the PIIX4 Power Management function
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for (devfn = 0; devfn < 256; devfn++)
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{
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pci_conf1_read_config_dword(0, devfn, 0, &val);
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if (val == 0x71138086)
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break;
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}
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if (devfn == 256)
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return(1);
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// Get SMBus IO Base register
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pci_conf1_read_config_word(0, devfn, 0x90, &baseaddr);
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baseaddr &= 0xfff0;
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printf("got devfn 0x%x baseaddr 0x%x\n", devfn, baseaddr);
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if (!baseaddr) // Still in default
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return(2);
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pci_conf1_write_config_word(0, devfn, 0xd2, (4<<1)|1);
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/* Communicate on the SMBus through the SMBus IO Space Registers
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* See the System Management Bus Specification [1] for general
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* information about the bus. See the PIIX4 datasheet [2] for
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* information about the SMBus IO Space Registers (p. 148) */
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waitbusy(baseaddr);
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for(i = 0x1; i < 0x100; i += 2) {
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if (i == 0xd3)
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continue;
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outb(HOST_RESET, baseaddr + SMBHSTSTS);
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outb(i, baseaddr + SMBHSTADD);
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outb(0x3, baseaddr + SMBHSTCMD);
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outb(0, baseaddr + SMBHSTDAT0);
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outb((2<<2)|(1<<6), baseaddr + SMBHSTCTL);
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/* Check DIMM status once */
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status = waitstatus(baseaddr);
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printf("status 0x%x ", status);
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if (status == 4) {printf("no device at 0x%x\n", i);}
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else printf("device at 0x%x\n", i);
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}
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#if 0
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#endif
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/* Select the DIMM chip to read SPD data (cycle through all of them) */
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for (dimm = 0; dimm < 8; dimm++)
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{
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/* Reset the controller status before using */
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outb(HOST_RESET, baseaddr + SMBHSTSTS);
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printf("DIMM #%d:\n", dimm);
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/* Set up SPD for READ's */
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outb(DIMM_BASE | (dimm << 1) | READ_CMD, baseaddr + SMBHSTADD);
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/* For each piece of Data below, we select the data number in the
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Command Register (SBDHSTCMD) and tell the Control Register
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(SMBHSTCTL) we are reading a byte of data. Then grab the data from
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data register 0 (SMBHSTDAT0).
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*/
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#if 0
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/* Specification Revision */
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outb(SPD_REV, baseaddr + SMBHSTCMD);
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outb(0x48, baseaddr + SMBHSTCTL);
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#endif
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outb(0x3, baseaddr + SMBHSTCMD);
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outb(0, baseaddr + SMBHSTDAT0);
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outb((2<<2)|(1<<6), baseaddr + SMBHSTCTL);
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/* Check DIMM status once */
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status = waitstatus(baseaddr);
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if (status & 0x04)
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{
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printf("No SPD present at DIMM\n\n");
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continue;
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}
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else if (error_check(baseaddr)) return (3);
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data = inb(baseaddr + SMBHSTDAT0);
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printf("SPD Revision: %d.%d\n", (data & 0xf0) >> 4, data & 0x0f);
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/* Memory Type */
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outb(HOST_RESET, baseaddr + SMBHSTSTS);
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outb(MEM_TYPE, baseaddr + SMBHSTCMD);
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outb(0x48, baseaddr + SMBHSTCTL);
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if (error_check(baseaddr)) return(4);
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data = inb(baseaddr + SMBHSTDAT0);
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switch(data)
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{
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case 0x02:
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{
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printf("DIMM #%d contains EDO\n", dimm);
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break;
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}
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case 0x04:
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{
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printf("DIMM #%d contains SDRAM\n", dimm);
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break;
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}
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default:
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{
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printf("DIMM %d contains unknown (0x%02X) type\n", dimm, data);
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break;
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}
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}
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/* Memory Size */
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/* Start w/ number of module rows */
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outb(HOST_RESET, baseaddr + SMBHSTSTS);
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outb(NUM_MOD_ROWS, baseaddr + SMBHSTCMD);
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outb(0x48, baseaddr + SMBHSTCTL);
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if (error_check(baseaddr)) return(5);
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rows = inb(baseaddr + SMBHSTDAT0);
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if (rows == 0)
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{
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printf("Undefined number of rows");
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}
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else
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{
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printf("%d module rows on DIMM\n", rows);
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}
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/* Now do size of row */
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outb(HOST_RESET, baseaddr + SMBHSTSTS);
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outb(BANK_DENSITY, baseaddr + SMBHSTCMD);
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outb(0x48, baseaddr + SMBHSTCTL);
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if (error_check(baseaddr)) return(6);
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density = inb(baseaddr + SMBHSTDAT0);
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switch (density)
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{
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case 0x01:
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case 0x02:
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case 0x04:
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case 0x08:
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case 0x10:
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case 0x20:
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case 0x40:
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case 0x80:
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{
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printf("DIMM has %dMByte per row.\n", density << 2);
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printf("DIMM has %dMByte total.\n", (density << 2) * rows);
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break;
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}
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default:
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{
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printf("DIMM has mixed memory per row.\n");
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printf("Unknown total memory.\n");
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break;
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}
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}
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}
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return(0);
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}
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/* Waitbusy... could possibly hang CPU, so insert timeout */
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inline void waitbusy (unsigned short baseaddr)
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{
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while(1)
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if ( !(inb(baseaddr + SMBHSTSTS) & 0x01) )
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return;
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}
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/* waitstatus... could also hang CPU */
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inline int waitstatus (unsigned short baseaddr)
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{
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int status;
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do
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status = inb(baseaddr + SMBHSTSTS);
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while ( (status & 0x01) != 0 || status == 0);
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return (status);
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}
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/* Error check for transaction errors */
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int error_check (unsigned short baseaddr)
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{
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int status;
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status = waitstatus(baseaddr);
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if ( !(status & 0x02) )
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{
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printf("Transaction error 0x%02X\n", status);
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return(1);
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}
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return(0);
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}
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