From ceabf57ca78449fa6e9cfd212bdf4774706de92f Mon Sep 17 00:00:00 2001 From: David Hendricks Date: Mon, 12 Aug 2013 15:06:45 -0700 Subject: [PATCH] exynos5420: Correct the 600MHz PMS value In UM ver0.02, 600MHz clock PMS values differs from what is programed currently. Though this also results in 600MHz clock, but it is better to match what UM says. This patch chnage this as per UM This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3 (Note: we already used the correct 600MHz value for KPLL) Signed-off-by: David Hendricks BUG=none BRANCH=none TEST=built and booted on Pit Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5 Reviewed-on: https://gerrit.chromium.org/gerrit/65726 Reviewed-by: Ronald G. Minnich Tested-by: Ronald G. Minnich Commit-Queue: David Hendricks Tested-by: David Hendricks --- src/cpu/samsung/exynos5420/clock_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock_init.c b/src/cpu/samsung/exynos5420/clock_init.c index 658b2559e8..eeeda90bf2 100644 --- a/src/cpu/samsung/exynos5420/clock_init.c +++ b/src/cpu/samsung/exynos5420/clock_init.c @@ -81,7 +81,7 @@ void system_clock_init(void) /* Set KPLL*/ writel(KPLL_CON1_VAL, &clk->kpll_con1); - val = set_pll(0xc8, 0x2, 0x2); + val = set_pll(0x190, 0x4, 0x2); writel(val, &clk->kpll_con0); while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0) ;