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haswell: update pei_data data structure

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Update and use the new pei_data data structure. Now that the
reference code is fixed it's possible to properly disable/enable
the USB2 and USB3 ports correctly.

BUG=None
BRANCH=None
TEST=emerge slippy. All USB connections available to me still work. Both
     USB3 and USB2. Other boards assumed to work.

Change-Id: I075c646e7574be354420b6e59507e8917a97d0f0
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/56594
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
This commit is contained in:
Aaron Durbin 2013-05-23 15:57:46 -05:00 • committed by ChromeBot
commit ce8fd58e93
5 changed files with 106 additions and 75 deletions
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49
src/mainboard/intel/baskingridge/romstage.c
View file

@ -93,21 +93,40 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 0,
dimm_channel1_disabled: 0,
max_ddr3_freq: 1600,
usb_port_config: {
{ 1, 0, 0x0040 }, /* P0: Back USB3 port (OC0) */
{ 1, 0, 0x0040 }, /* P1: Back USB3 port (OC0) */
{ 1, 1, 0x0040 }, /* P2: Flex Port on bottom (OC1) */
{ 1, 8, 0x0040 }, /* P3: Docking connector (no OC) */
{ 1, 8, 0x0040 }, /* P4: Mini PCIE (no OC) */
{ 1, 1, 0x0040 }, /* P5: USB eSATA header (OC1) */
{ 1, 3, 0x0040 }, /* P6: Front Header J8H2 (OC3) */
{ 1, 3, 0x0040 }, /* P7: Front Header J8H2 (OC3) */
{ 1, 4, 0x0040 }, /* P8: USB/LAN Jack (OC4) */
{ 1, 4, 0x0040 }, /* P9: USB/LAN Jack (OC4) */
{ 1, 5, 0x0040 }, /* P10: Front Header J7H3 (OC5) */
{ 1, 5, 0x0040 }, /* P11: Front Header J7H3 (OC5) */
{ 1, 6, 0x0040 }, /* P12: USB/DP Jack (OC6) */
{ 1, 6, 0x0040 }, /* P13: USB/DP Jack (OC6) */
{ 0x40, 1, 0 }, /* P0: */
{ 0x40, 1, 0 }, /* P1: */
{ 0x40, 1, 0 }, /* P2: */
{ 0x40, 1, 0 }, /* P3: */
{ 0x40, 1, 0 }, /* P4: */
{ 0x40, 1, 0 }, /* P5: */
{ 0x40, 1, 0 }, /* P6: */
{ 0x40, 0, 0 }, /* P7: Disable SDCARD due to hang */
},
usb2_ports: {
/* Length, Enable, OCn# */
{ 0x0040, 1, 0 }, /* P0: Back USB3 port (OC0) */
{ 0x0040, 1, 0 }, /* P1: Back USB3 port (OC0) */
{ 0x0040, 1, 1 }, /* P2: Flex Port on bottom (OC1) */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P3: Dock connector */
{ 0x0040, 1, USB_OC_PIN_SKIP }, /* P4: Mini PCIE */
{ 0x0040, 1, 1 }, /* P5: USB eSATA header (OC1) */
{ 0x0040, 1, 3 }, /* P6: Front Header J8H2 (OC3) */
{ 0x0040, 1, 3 }, /* P7: Front Header J8H2 (OC3) */
{ 0x0040, 1, 4 }, /* P8: USB/LAN Jack (OC4) */
{ 0x0040, 1, 4 }, /* P9: USB/LAN Jack (OC4) */
{ 0x0040, 1, 5 }, /* P10: Front Header J7H3 (OC5) */
{ 0x0040, 1, 5 }, /* P11: Front Header J7H3 (OC5) */
{ 0x0040, 1, 6 }, /* P12: USB/DP Jack (OC6) */
{ 0x0040, 1, 6 }, /* P13: USB/DP Jack (OC6) */
},
usb3_ports: {
/* Enable, OCn# */
{ 1, 0 }, /* P1; */
{ 1, 0 }, /* P2; */
{ 1, 0 }, /* P3; */
{ 1, 0 }, /* P4; */
{ 1, 0 }, /* P6; */
{ 1, 0 }, /* P6; */
},
};

32
src/mainboard/intel/wtm2/romstage.c
View file

@ -98,21 +98,23 @@ void mainboard_romstage_entry(unsigned long bist)
dimm_channel0_disabled: 2,
dimm_channel1_disabled: 2,
max_ddr3_freq: 1600,
usb_port_config: {
{ 1, 0, 0x0040 }, /* P0: */
{ 1, 0, 0x0040 }, /* P1: */
{ 1, 0, 0x0040 }, /* P2: */
{ 1, 0, 0x0040 }, /* P3: */
{ 1, 0, 0x0040 }, /* P4: */
{ 1, 0, 0x0040 }, /* P5: */
{ 1, 0, 0x0040 }, /* P6: */
{ 0, 0, 0x0040 }, /* P7: Disable SDCARD due to hang */
{ 1, 0, 0x0040 }, /* P8: */
{ 1, 0, 0x0040 }, /* P9: */
{ 1, 0, 0x0040 }, /* P10: */
{ 1, 0, 0x0000 }, /* P11: */
{ 1, 0, 0x0040 }, /* P12: */
{ 1, 0, 0x0040 }, /* P13: */
usb2_ports: {
/* Length, Enable, OCn# */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P0: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P1: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P2: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P3: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P4: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P5: */
{ 0x40, 1, USB_OC_PIN_SKIP }, /* P6: */
{ 0x40, 0, USB_OC_PIN_SKIP }, /* P7: Disable SDCARD due to hang */
},
usb3_ports: {
/* Enable, OCn# */
{ 1, USB_OC_PIN_SKIP }, /* P1; */
{ 1, USB_OC_PIN_SKIP }, /* P2; */
{ 1, USB_OC_PIN_SKIP }, /* P3; */
{ 1, USB_OC_PIN_SKIP }, /* P4; */
},
};