From ce5a1e8a5113277493d2d9b770784e3bc96d426e Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Wed, 9 Jul 2025 16:12:08 +0800 Subject: [PATCH] mb/google/brox: Create caboc variant Create the caboc variant of the brox reference board by copying the template files to a new directory named for the variant. BUG=b:420796212 TEST=util/abuild/abuild -p none -t google/brox -x -a make sure the build includes GOOGLE_CABOC. Change-Id: I424933574873defe5289fbe7309270583cb8a49e Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/88379 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/brox/Kconfig | 15 + src/mainboard/google/brox/Kconfig.name | 3 + .../google/brox/variants/caboc/Makefile.mk | 11 + .../google/brox/variants/caboc/data.vbt | Bin 0 -> 8704 bytes .../google/brox/variants/caboc/fw_config.c | 78 ++++ .../google/brox/variants/caboc/gpio.c | 188 ++++++++ .../brox/variants/caboc/include/variant/ec.h | 8 + .../variants/caboc/include/variant/gpio.h | 14 + .../variants/caboc/include/variant/hda_verb.h | 123 ++++++ .../google/brox/variants/caboc/memory.c | 106 +++++ .../brox/variants/caboc/memory/Makefile.mk | 10 + .../caboc/memory/dram_id.generated.txt | 14 + .../variants/caboc/memory/mem_parts_used.txt | 8 + .../brox/variants/caboc/overridetree.cb | 403 ++++++++++++++++++ .../google/brox/variants/caboc/ramstage.c | 43 ++ .../google/brox/variants/caboc/variant.c | 25 ++ 16 files changed, 1049 insertions(+) create mode 100644 src/mainboard/google/brox/variants/caboc/Makefile.mk create mode 100644 src/mainboard/google/brox/variants/caboc/data.vbt create mode 100644 src/mainboard/google/brox/variants/caboc/fw_config.c create mode 100644 src/mainboard/google/brox/variants/caboc/gpio.c create mode 100644 src/mainboard/google/brox/variants/caboc/include/variant/ec.h create mode 100644 src/mainboard/google/brox/variants/caboc/include/variant/gpio.h create mode 100644 src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h create mode 100644 src/mainboard/google/brox/variants/caboc/memory.c create mode 100644 src/mainboard/google/brox/variants/caboc/memory/Makefile.mk create mode 100644 src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/brox/variants/caboc/overridetree.cb create mode 100644 src/mainboard/google/brox/variants/caboc/ramstage.c create mode 100644 src/mainboard/google/brox/variants/caboc/variant.c diff --git a/src/mainboard/google/brox/Kconfig b/src/mainboard/google/brox/Kconfig index 9a22731a94..c37ccacb21 100644 --- a/src/mainboard/google/brox/Kconfig +++ b/src/mainboard/google/brox/Kconfig @@ -95,6 +95,18 @@ config BOARD_GOOGLE_JUBILANT select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS +config BOARD_GOOGLE_CABOC + select BOARD_GOOGLE_BASEBOARD_BROX + select CHROMEOS_WIFI_SAR if CHROMEOS + select DRIVERS_WWAN_FM350GL + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select MAINBOARD_HAS_GOOGLE_STRAUSS_KEYBOARD + select RT8168_GEN_ACPI_POWER_RESOURCE + select RT8168_GET_MAC_FROM_VPD + select RT8168_SET_LED_MODE + select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS + if BOARD_GOOGLE_BROX_COMMON config BASEBOARD_DIR @@ -125,6 +137,7 @@ config PL4_LIMIT_FOR_CRITICAL_BAT_BOOT int default 9 if BOARD_GOOGLE_BROX default 9 if BOARD_GOOGLE_BROX_RTK_EC + default 14 if BOARD_GOOGLE_CABOC default 14 if BOARD_GOOGLE_JUBILANT default 40 if BOARD_GOOGLE_LOTSO help @@ -163,6 +176,7 @@ config MAINBOARD_PART_NUMBER default "Brox_Ec_Ish" if BOARD_GOOGLE_BROX_EC_ISH default "Brox_Ti_Pdc" if BOARD_GOOGLE_BROX_TI_PDC default "Brox_Rtk_Ec" if BOARD_GOOGLE_BROX_RTK_EC + default "Caboc" if BOARD_GOOGLE_CABOC default "Greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC default "Jubilant" if BOARD_GOOGLE_JUBILANT default "Lotso" if BOARD_GOOGLE_LOTSO @@ -173,6 +187,7 @@ config VARIANT_DIR BOARD_GOOGLE_BROX_EC_ISH || \ BOARD_GOOGLE_BROX_TI_PDC || \ BOARD_GOOGLE_BROX_RTK_EC + default "caboc" if BOARD_GOOGLE_CABOC default "lotso" if BOARD_GOOGLE_LOTSO default "greenbayupoc" if BOARD_GOOGLE_GREENBAYUPOC default "jubilant" if BOARD_GOOGLE_JUBILANT diff --git a/src/mainboard/google/brox/Kconfig.name b/src/mainboard/google/brox/Kconfig.name index 7820878bd2..2d67ec094d 100644 --- a/src/mainboard/google/brox/Kconfig.name +++ b/src/mainboard/google/brox/Kconfig.name @@ -14,6 +14,9 @@ config BOARD_GOOGLE_BROX_EC_ISH config BOARD_GOOGLE_BROX_TI_PDC bool "-> Brox TI PDC" +config BOARD_GOOGLE_CABOC + bool "-> Caboc" + config BOARD_GOOGLE_GREENBAYUPOC bool "-> Greenbayupoc" diff --git a/src/mainboard/google/brox/variants/caboc/Makefile.mk b/src/mainboard/google/brox/variants/caboc/Makefile.mk new file mode 100644 index 0000000000..06ae480be1 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/Makefile.mk @@ -0,0 +1,11 @@ +## SPDX-License-Identifier: GPL-2.0-only + +bootblock-y += gpio.c + +romstage-y += gpio.c +romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += variant.c +ramstage-y += gpio.c +ramstage-y += ramstage.c diff --git a/src/mainboard/google/brox/variants/caboc/data.vbt b/src/mainboard/google/brox/variants/caboc/data.vbt new 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*/ + PAD_NC(GPP_D8, NONE), + /* GPP_D9 : FP_RST_ODL */ + PAD_NC(GPP_D9, NONE), + /* GPP_D11 : [] ==> EN_FP_PWR */ + PAD_NC(GPP_D11, NONE), + /* GPP_E4 : FP GSPI INT */ + PAD_NC(GPP_E4, NONE), + /* GPP_F11 : FP GSPI CLK */ + PAD_NC(GPP_F11, NONE), + /* GPP_F12 : FP GSPI DO */ + PAD_NC(GPP_F12, NONE), + /* GPP_F13 : FP GSPI DI */ + PAD_NC(GPP_F13, NONE), + /* GPP_F16 : FP GSPI CS */ + PAD_NC(GPP_F16, NONE), +}; + +static const struct pad_config lte_disable_pads[] = { + /* GPP_A17 :WWAN_TRANSMIT_OFF */ + PAD_NC(GPP_A17, NONE), + /* GPP_A21 : WWAN_ASPM_EXIT */ + PAD_NC(GPP_A21, NONE), + /* GPP_D4 : WWAN_GPS_XMIT_L */ + PAD_NC(GPP_D4, NONE), + /* GPP_D15 : WWAN_CONFIG_3 */ + PAD_NC(GPP_D15, NONE), + /* GPP_D16 : WWAN_CONFIG_2 */ + PAD_NC(GPP_D16, NONE), + /* GPP_D19 : WWAN_FWUPD# */ + PAD_NC(GPP_D19, NONE), + /* GPP_E5 : WWAN_WAKE# */ + PAD_NC(GPP_E5, NONE), + /* GPP_F19 : PCIE_CLKREQ_WWAN */ + PAD_NC(GPP_F19, NONE), + /* GPP_F21 : WWAN_OFF# */ + PAD_NC(GPP_F21, NONE), +}; + +static const struct pad_config nvme_disable_pads[] = { + /* GPP_F9 : SSD_PERST_L */ + PAD_NC(GPP_F9, NONE), + /* GPP_D5 : SSD_CLKREQ_ODL */ + PAD_NC(GPP_D5, NONE), +}; + +static void fw_config_handle(void *unused) +{ + if (!fw_config_is_provisioned()) { + printk(BIOS_WARNING, "FW_CONFIG is unprovisioned. Skip disable device's pads.\n"); + return; + } + + if (fw_config_probe(FW_CONFIG(FP, FP_ABSENT))) { + printk(BIOS_INFO, "Disable Fingerprint GPIOs by fw_config.\n"); + gpio_configure_pads(fp_disable_pads, ARRAY_SIZE(fp_disable_pads)); + } + + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins by fw_config.\n"); + gpio_configure_pads(lte_disable_pads, ARRAY_SIZE(lte_disable_pads)); + } + + if (!fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { + printk(BIOS_INFO, "Disable NVMe GPIO pins by fw_config.\n"); + gpio_configure_pads(nvme_disable_pads, ARRAY_SIZE(nvme_disable_pads)); + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fw_config_handle, NULL); diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c new file mode 100644 index 0000000000..e2127d0ceb --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/gpio.c @@ -0,0 +1,188 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* GPP_A12 : [NF1: SATAXPCIE1 NF2: SATAGP1 NF4: SRCCLKREQ9B# NF6: USB_C_GPP_A12] ==> KBL_DET(reserve) */ + PAD_NC(GPP_A12, NONE), + /* GPP_A14 : [NF1: USB_OC1# NF2: DDSP_HPD3 NF4: DISP_MISC3 NF6: USB_C_GPP_A14] ==> NC */ + PAD_NC(GPP_A14, NONE), + /* GPP_A15 : [NF1: USB_OC2# NF2: DDSP_HPD4 NF4: DISP_MISC4 NF6: USB_C_GPP_A15] ==> NC */ + PAD_NC(GPP_A15, NONE), + /* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> WWAN_TRANSMIT_OFF(WAN_RF_DISABLE_ODL) */ + PAD_CFG_GPO(GPP_A17, 1, DEEP), + /* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + + /* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> WWAN_GPS_XMIT_OFF */ + PAD_CFG_GPO(GPP_D4, 0, DEEP), + /* GPP_D5 : SRCCLKREQ0_L ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), + /* GPP_D7 : SRCCLKREQ2_L ==> PCIE_CLKREQ_LAN */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* GPP_D8 : [NF1: SRCCLKREQ3# NF6: USB_C_GPP_D8] ==> PCH_FP_BOOT0 */ + PAD_CFG_GPO_LOCK(GPP_D8, 0, LOCK_CONFIG), + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */ + PAD_CFG_GPO_LOCK(GPP_D9, 0, LOCK_CONFIG), + /* GPP_D10 : [NF1: ISH_SPI_CLK NF2: DDP3_CTRLDATA NF4: TBT_LSX2_RXD NF5: BSSB_LS2_TX NF6: USB_C_GPP_D10 NF7: GSPI2_CLK] ==> USB_C2_LSX_RX_STRAP(NC) */ + PAD_NC(GPP_D10, NONE), + /* GPP_D11 : [] ==> EN_FP_POWER*/ + PAD_CFG_GPO_LOCK(GPP_D11, 0, LOCK_CONFIG), + /* GPP_D15 : ISH_UART0_RTS_L/I2C7B_SDA ==> WWAN_CONFIG_3 */ + PAD_CFG_GPI_LOCK(GPP_D15, NONE, LOCK_CONFIG), + /* GPP_D16 : ISH_UART0_CTS_L/I2C7B_SCL ==> WWAN_CONFIG_2 */ + PAD_CFG_GPI_LOCK(GPP_D16, NONE, LOCK_CONFIG), + /* GPP_D18 : UART1_TXD/ISH_UART1_RXD ==> LANLINK_STATUS */ + PAD_CFG_GPI(GPP_D18, NONE, DEEP), + /* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAN_FWUPD#(WWAN_RST_L) */ + PAD_CFG_GPO(GPP_D19, 1, DEEP), + + /* GPP_E4 : [NF1: DEVSLP0 NF6: USB_C_GPP_E4 NF7: SRCCLK_OE9#] ==> GSPI_FPMCU_INT_L */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E4, NONE, PWROK, LEVEL, INVERT), + /* GPP_E5 : [NF1: DEVSLP1 NF6: USB_C_GPP_E5 NF7: SRCCLK_OE6#] ==> WWAN_WAKE# */ + PAD_CFG_GPI_INT(GPP_E5, NONE, PLTRST, EDGE_SINGLE), + /* GPP_E7 : [NF1: PROC_GP1 NF6: USB_C_GPP_E7] ==> EN_UCAM_PWR*/ + PAD_CFG_GPO(GPP_E7, 1, DEEP), + /* GPP_E18 : [NF1: DDP1_CTRLCLK NF4: TBT_LSX0_TXD NF5: BSSB_LS0_RX NF6: USB_C_GPP_E18] ==> NC */ + PAD_NC(GPP_E18, NONE), + /* GPP_E19 : [NF1: DDP1_CTRLDATA NF4: TBT_LSX0_RXD NF5: BSSB_LS0_TX NF6: USB_C_GPP_E19] ==> USB_C0_LSX_RX_STRAP(NC) */ + PAD_NC(GPP_E19, NONE), + + /* GPP_F11 : [NF3: THC1_SPI2_CLK NF4: GSPI1_CLK NF6: USB_C_GPP_F11] ==> GSPI_PCH_CLK_FPMCU_R */ + PAD_CFG_NF_LOCK(GPP_F11, NONE, NF4, LOCK_CONFIG), + /* GPP_F12 : [NF1: GSXDOUT NF3: THC1_SPI2_IO0 NF4: GSPI1_MOSI NF5: I2C1A_SCL NF6: USB_C_GPP_F12] ==> GSPI_PCH_DO_FPMCU_DI_R */ + PAD_CFG_NF_LOCK(GPP_F12, NONE, NF4, LOCK_CONFIG), + /* GPP_F13 : [NF1: GSXSLOAD NF3: THC1_SPI2_IO1 NF4: GSPI1_MISIO NF5: I2C1A_SDA NF6: USB_C_GPP_F13] ==> GSPI_PCH_DI_FPMCU_DO */ + PAD_CFG_NF_LOCK(GPP_F13, NONE, NF4, LOCK_CONFIG), + /* GPP_F15 : [NF1: GSXSRESET# NF3: THC1_SPI2_IO3 NF6: USB_C_GPP_F15] ==> NC */ + PAD_NC(GPP_F15, NONE), + /* GPP_F16 : [NF1: GSXCLK NF3: THC1_SPI2_CS# NF4: GSPI1_CS0# NF6: USB_C_GPP_F16] ==> GSPI_PCH_CS_FPMCU_R_L */ + PAD_CFG_NF_LOCK(GPP_F16, NONE, NF4, LOCK_CONFIG), + /* GPP_F19 : SRCCLKREQ6 ==> PCIE_CLKREQ_WWAN */ + PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), + /* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L)*/ + PAD_CFG_GPO(GPP_F21, 1, DEEP), +}; + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + + /* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */ + PAD_CFG_GPO(GPP_F21, 0, DEEP), + /* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */ + PAD_CFG_GPO(GPP_D19, 0, DEEP), + + /* + * FP_RST_ODL comes out of reset as hi-z and does not have an external pull-down. + * To ensure proper power sequencing for the FPMCU device, reset signal is driven low + * early on in bootblock, followed by enabling of power. Reset signal is deasserted + * later on in ramstage. Since reset signal is asserted in bootblock, it results in + * FPMCU not working after a S3 resume. This is a known issue. + */ + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), + /* GPP_D11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), + + /* GPP_E2 : THC0_SPI1_IO3 ==> GSC_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_E2, NONE, PLTRST, LEVEL, INVERT), + /* GPP_E8 : GPP_E8 ==> PCH_WP_OD */ + PAD_CFG_GPI_LOCK(GPP_E8, NONE, LOCK_CONFIG), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 0, DEEP), + /* GPP_H8 : [NF1: I2C4_SDA NF2: CNV_MFUART2_RXD NF6: USB_C_GPP_H8] ==> PCH_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), + /* GPP_H9 : [NF1: I2C4_SCL NF2: CNV_MFUART2_TXD] ==> PCH_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_PCH_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, PLTRST, NF2), + /* H11 : UART0_TXD ==> UART_PCH_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, PLTRST, NF2), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), + + /* CPU PCIe vGPIO for RP2 */ + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_32, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_33, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_34, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_35, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_36, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_37, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_38, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_39, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_40, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_41, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_42, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_43, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_44, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_45, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_46, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_47, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_72, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_73, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_74, NONE, PLTRST, NF1), + PAD_CFG_NF_VWEN(GPP_vGPIO_PCIE_75, NONE, PLTRST, NF1), +}; + +static const struct pad_config romstage_gpio_table[] = { + /* GPP_D9 : [NF1: ISH_SPI_CS# NF2: DDP3_CTRLCLK NF4: TBT_LSX2_TXD NF5: BSSB_LS2_RX NF6: USB_C_GPP_D9 NF7: GSPI2_CS0#] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_D9, 0, DEEP), + /* GPP_D11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_D11, 0, DEEP), + + /* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */ + PAD_CFG_GPO(GPP_F21, 1, DEEP), + /* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */ + PAD_CFG_GPO(GPP_D19, 0, DEEP), + + /* GPP_E10 : THC0_SPI1_CS_L/GSPI0_CS0_L ==> MEM_STRAP_3 */ + PAD_CFG_GPI(GPP_E10, NONE, PLTRST), + /* GPP_E12 : THC0_SPI1_IO1/I2C0A_SDA/GSPI0_MISO ==> MEM_STRAP_1 */ + PAD_CFG_GPI(GPP_E12, NONE, PLTRST), + /* GPP_E13 : THC0_SPI1_IO0/I2C0A_SCL/GSPI0_MOSI ==> MEM_STRAP_2 */ + PAD_CFG_GPI(GPP_E13, NONE, PLTRST), + /* GPP_E15 : SRCCLK_OE8_L ==> MEM_STRAP_0 */ + PAD_CFG_GPI(GPP_E15, NONE, PLTRST), + /* GPP_F7 : [NF6: USB_C_GPP_F7] ==> EN_PP3300_TCHSCR */ + PAD_CFG_GPO(GPP_F7, 1, PLTRST), + /* GPP_F9 : [NF1: BOOTMPC NF6: USB_C_GPP_F9] ==> SSD_PERST_L */ + PAD_CFG_GPO(GPP_F9, 1, DEEP), + /* GPP_F17 : [NF3: THC1_SPI2_RST# NF6: USB_C_GPP_F17] ==> TCHSCR_RST_L */ + PAD_CFG_GPO(GPP_F17, 0, DEEP), + /* GPP_S0 : SNDW0_CLL/I2S1_SCLK ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_S0, NONE, DEEP), +}; + +const struct pad_config *variant_gpio_override_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} + +const struct pad_config *variant_romstage_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(romstage_gpio_table); + return romstage_gpio_table; +} + +static const struct cros_gpio cros_gpios[] = { + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), +}; + +DECLARE_CROS_GPIOS(cros_gpios); diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/ec.h b/src/mainboard/google/brox/variants/caboc/include/variant/ec.h new file mode 100644 index 0000000000..4fc0622f15 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h b/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h new file mode 100644 index 0000000000..8fbc069648 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/include/variant/gpio.h @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef __MAINBOARD_GPIO_H__ +#define __MAINBOARD_GPIO_H__ + +#include + +#define T1_OFF_MS 16 +#define T2_OFF_MS 2 +#define WWAN_FCPO GPP_F21 +#define WWAN_RST GPP_D19 +#define WWAN_PERST GPP_A21 + +#endif /* __MAINBOARD_GPIO_H__ */ diff --git a/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h new file mode 100644 index 0000000000..9435ad7d46 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/include/variant/hda_verb.h @@ -0,0 +1,123 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_HDA_VERB_H +#define MAINBOARD_HDA_VERB_H + +#include + +const u32 cim_verb_data[] = { + /* coreboot specific header */ + 0x10ec0236, // Codec Vendor / Device ID: Realtek ALC236 + 0x103C8C60, // Subsystem ID + 0x00000017, // Number of jacks (NID entries) + + AZALIA_RESET(0x1), + /* NID 0x01, HDA Codec Subsystem ID Verb table */ + AZALIA_SUBVENDOR(0, 0x103C8C60), + + /* Pin Widget Verb Table */ + + /* + * DMIC + * Requirement is to use PCH DMIC. Hence, + * commented out codec's Internal DMIC. + * AZALIA_PIN_CFG(0, 0x12, 0x90A60130), + * AZALIA_PIN_CFG(0, 0x13, 0x40000000), + */ + + /* Pin widget 0x14 - Front (Port-D) */ + AZALIA_PIN_CFG(0, 0x14, 0x90170110), + /* Pin widget 0x18 - NPC */ + AZALIA_PIN_CFG(0, 0x18, 0x411111F0), + /* Pin widget 0x19 - MIC2 (Port-F) */ + AZALIA_PIN_CFG(0, 0x19, 0x03A11020), + /* Pin widget 0x1A - LINE1 (Port-C) */ + AZALIA_PIN_CFG(0, 0x1a, 0x411111F0), + /* Pin widget 0x1B - NPC */ + AZALIA_PIN_CFG(0, 0x1b, 0x411111F0), + /* Pin widget 0x1D - BEEP-IN */ + AZALIA_PIN_CFG(0, 0x1d, 0x40600001), + /* Pin widget 0x1E - NPC */ + AZALIA_PIN_CFG(0, 0x1e, 0x411111F0), + /* Pin widget 0x21 - HP1-OUT (Port-I) */ + AZALIA_PIN_CFG(0, 0x21, 0x03211040), + + /* + * Widget node 0x20 - 1 + */ + 0x0205003C, + 0x02040354, + 0x0205003C, + 0x02040314, + /* + * Widget node 0x20 - 2 + * Set JD2 pull high + */ + 0x0205001B, + 0x02040A4B, + 0x0205000B, + 0x02047778, + /* + * Widget node 0x20 - 3 + */ + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409A3, + /* disable EQ first */ + 0x05350000, + 0x0534201A, + /* Left Channel */ + 0x0535001d, + 0x05340800, + 0x0535001e, + 0x05340800, + 0x05350003, + 0x05341F7B, + 0x05350004, + 0x05340000, + /* Right Channel */ + 0x05450000, + 0x05442000, + 0x0545001d, + 0x05440800, + 0x0545001e, + 0x05440800, + 0x05450003, + 0x05441F7B, + 0x05450004, + 0x05440000, + /* enable EQ */ + 0x05350000, + 0x0534E01A, + /* 1.8W/4ohm */ + 0x02050038, + 0x02047901, + /* AGC Enable */ + 0x0205004C, + 0x0204465C, + 0x02050016, + 0x02044E50, + 0x02050020, + 0x020451FF, + /* Headphone Pop */ + 0x05750007, + 0x057412B2, +}; + +const u32 pc_beep_verbs[] = { + /* Dos beep path - 1 */ + 0x02050036, + 0x02047151, + 0x02050010, + 0x02040020, + /* Dos beep path - 2 */ + 0x0143B000, + 0x01470740, + 0x01470C02, + 0x01470C02, +}; + +AZALIA_ARRAY_SIZES; + +#endif diff --git a/src/mainboard/google/brox/variants/caboc/memory.c b/src/mainboard/google/brox/variants/caboc/memory.c new file mode 100644 index 0000000000..24d625b157 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/memory.c @@ -0,0 +1,106 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +static const struct mb_cfg baseboard_memcfg = { + .type = MEM_TYPE_LP5X, + + /* Leave Rcomp unspecified to use the FSP optimized defaults */ + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 4, 7, 5, 6, 0, 1, 2, 3, }, + .dq1 = { 8, 11, 9, 10, 13, 14, 15, 12, }, + }, + .ddr1 = { + .dq0 = { 1, 2, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, + }, + .ddr2 = { + .dq0 = { 0, 3, 2, 1, 6, 5, 7, 4, }, + .dq1 = { 14, 12, 15, 13, 8, 10, 9, 11, }, + }, + .ddr3 = { + .dq0 = { 5, 7, 4, 6, 2, 0, 1, 3, }, + .dq1 = { 10, 9, 11, 8, 12, 15, 13, 14, }, + }, + .ddr4 = { + .dq0 = { 4, 6, 5, 7, 3, 2, 1, 0, }, + .dq1 = { 8, 11, 9, 10, 14, 13, 15, 12, }, + }, + .ddr5 = { + .dq0 = { 2, 1, 3, 0, 6, 4, 7, 5, }, + .dq1 = { 13, 15, 12, 14, 8, 11, 9, 10, }, + }, + .ddr6 = { + .dq0 = { 14, 12, 15, 13, 8, 11, 10, 9, }, + .dq1 = { 1, 2, 3, 0, 5, 6, 7, 4, }, + }, + .ddr7 = { + .dq0 = { 3, 6, 2, 7, 5, 0, 1, 4, }, + .dq1 = { 9, 8, 14, 15, 10, 12, 13, 11, }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 } + }, + + .lp5x_config = { + .ccc_config = 0x99, + }, + + .LpDdrDqDqsReTraining = 1, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_ULT_ULX, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &baseboard_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * MEM_STRAP_0 GPP_E15 + * MEM_STRAP_1 GPP_E12 + * MEM_STRAP_2 GPP_E13 + * MEM_STRAP_3 GPP_E10 + */ + gpio_t spd_gpios[] = { + GPP_E15, + GPP_E12, + GPP_E13, + GPP_E10, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* MEM_CH_SEL GPP_S0 */ + return gpio_get(GPP_S0); +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} diff --git a/src/mainboard/google/brox/variants/caboc/memory/Makefile.mk b/src/mainboard/google/brox/variants/caboc/memory/Makefile.mk new file mode 100644 index 0000000000..5d896055e9 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/memory/Makefile.mk @@ -0,0 +1,10 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brox/variants/caboc/memory src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = H9JCNNNBK3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-9.hex # ID = 1(0b0001) Parts = K3KL6L60GM-MGCT +SPD_SOURCES += spd/lp5/set-0/spd-11.hex # ID = 2(0b0010) Parts = MT62F1G32D2DS-023 WT:C, K3KL8L80EM-MGCU, H58G56CK8BX146 +SPD_SOURCES += spd/lp5/set-0/spd-10.hex # ID = 3(0b0011) Parts = MT62F2G32D4DS-023 WT:C, K3KL9L90EM-MGCU, H58G66CK8BX147 diff --git a/src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt b/src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fdd88ea78d --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/memory/dram_id.generated.txt @@ -0,0 +1,14 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# ./util/spd_tools/bin/part_id_gen adl lp5 src/mainboard/google/brox/variants/caboc/memory src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +H9JCNNNBK3MLYR-N6E 0 (0000) +K3KL6L60GM-MGCT 1 (0001) +MT62F1G32D2DS-023 WT:C 2 (0010) +K3KL8L80EM-MGCU 2 (0010) +H58G56CK8BX146 2 (0010) +MT62F2G32D4DS-023 WT:C 3 (0011) +K3KL9L90EM-MGCU 3 (0011) +H58G66CK8BX147 3 (0011) diff --git a/src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt b/src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt new file mode 100644 index 0000000000..91bbc50cbc --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/memory/mem_parts_used.txt @@ -0,0 +1,8 @@ +H9JCNNNBK3MLYR-N6E +K3KL6L60GM-MGCT +MT62F1G32D2DS-023 WT:C +K3KL8L80EM-MGCU +H58G56CK8BX146 +MT62F2G32D4DS-023 WT:C +K3KL9L90EM-MGCU +H58G66CK8BX147 diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb new file mode 100644 index 0000000000..1270765c9a --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb @@ -0,0 +1,403 @@ +fw_config + field DB_USB 0 1 + option DB_1A 0 + option DB_1A_LTE 1 + end + field WIFI_BT 2 2 + option WIFI_BT_CNVI 0 + option WIFI_BT_PCIE 1 + end + field STORAGE 3 4 + option STORAGE_UFS 1 + option STORAGE_NVME 2 + end + field KB_BL 5 5 + option KB_BL_ABSENT 0 + option KB_BL_PRESENT 1 + end + field FP 7 7 + option FP_ABSENT 0 + option FP_PRESENT 1 + end + field PANEL 8 10 + option TOUCH_UNKNOWN 0 + option TOUCH_ELAN_HID_I2C 1 + option TOUCH_G2TOUCH_HID_I2C 2 + end +end + +chip soc/intel/alderlake + register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Camera + register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C0 + register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A2(DB) + register "usb2_ports[3]" = "USB2_PORT_TYPE_C(OC_SKIP)" # USB2_C2 + register "usb2_ports[4]" = "USB2_PORT_EMPTY" # Disable USB2 Port + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Type-A Port A0(MLB) + register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port + register "usb2_ports[7]" = "USB2_PORT_EMPTY" # Disable USB2 Port + register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # WWAN + register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # M.2 Bluetooth + + register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port A2(DB) + register "usb3_ports[1]" = "USB3_PORT_EMPTY" # Disable USB3 Port + register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type A port A0(MLB) + register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable USB3 Port + + register "platform_pmax" = "208" + + device domain 0 on + device ref dtt on + chip drivers/intel/dptf + ## sensor information + register "options.tsr[0].desc" = ""DRAM_SOC"" + register "options.tsr[1].desc" = ""CPU-Inlet"" + register "options.tsr[2].desc" = ""Charger"" + register "options.tsr[3].desc" = ""5V regulator"" + + ## Passive Policy + register "policies.passive" = "{ + [0] = DPTF_PASSIVE(CPU, CPU, 97, 5000), + [1] = DPTF_PASSIVE(CPU, TEMP_SENSOR_0, 85, 5000), + [2] = DPTF_PASSIVE(CPU, TEMP_SENSOR_1, 85, 5000), + [3] = DPTF_PASSIVE(CHARGER, TEMP_SENSOR_2, 85, 5000), + [4] = DPTF_PASSIVE(CPU, TEMP_SENSOR_3, 85, 5000), + }" + + ## Critical Policy + register "policies.critical" = "{ + [0] = DPTF_CRITICAL(CPU, 105, SHUTDOWN), + [1] = DPTF_CRITICAL(TEMP_SENSOR_0, 95, SHUTDOWN), + [2] = DPTF_CRITICAL(TEMP_SENSOR_1, 95, SHUTDOWN), + [3] = DPTF_CRITICAL(TEMP_SENSOR_2, 95, SHUTDOWN), + [4] = DPTF_CRITICAL(TEMP_SENSOR_3, 95, SHUTDOWN), + }" + + register "controls.power_limits" = "{ + .pl1 = { + .min_power = 15000, + .max_power = 15000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 200, + }, + .pl2 = { + .min_power = 55000, + .max_power = 55000, + .time_window_min = 28 * MSECS_PER_SEC, + .time_window_max = 32 * MSECS_PER_SEC, + .granularity = 1000, + } + }" + + ## Charger Performance Control (Control, mA) + register "controls.charger_perf" = "{ + [0] = { 255, 1700 }, + [1] = { 24, 1500 }, + [2] = { 16, 1000 }, + [3] = { 8, 500 } + }" + + device generic 0 alias dptf_policy on end + end + end # DTT + device ref igpu on + chip drivers/gfx/generic + register "device_count" = "6" + # DDIA for eDP + register "device[0].name" = ""LCD0"" + register "device[0].type" = "panel" + # DDIB for HDMI + # If HDMI is not enumerated in the kernel, then no GFX device should be added for DDIB + register "device[1].name" = ""DD01"" + # TCP0 (DP-1) for port C0 + register "device[2].name" = ""DD02"" + register "device[2].use_pld" = "true" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + # TCP1 (DP-2) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP1 + register "device[3].name" = ""DD03"" + # TCP2 (DP-3) for port C2 + register "device[4].name" = ""DD04"" + register "device[4].use_pld" = "true" + register "device[4].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + # TCP3 (DP-4) is unused for any ports but still enumerated in the kernel, so GFX device is added for TCP3 + register "device[5].name" = ""DD05"" + device generic 0 on end + end + end # Integrated Graphics Device + device ref pch_espi on + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device ref pmc hidden + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + use usb2_port2 as usb2_port + use tcss_usb3_port1 as usb3_port + device generic 0 on end + end + chip drivers/intel/pmc_mux/conn + use usb2_port4 as usb2_port + use tcss_usb3_port3 as usb3_port + device generic 1 on end + end + end + end + end + device ref tcss_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref tcss_usb3_port3 on end + end + end + end + end + device ref xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Camera"" + register "type" = "UPC_TYPE_INTERNAL" + register "has_power_resource" = "true" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E7)" + device ref usb2_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" + device ref usb2_port2 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A2 (DB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb2_port3 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C2 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" + device ref usb2_port4 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb2_port6 on end + end + chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port9 on + probe DB_USB DB_1A_LTE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Bluetooth"" + register "type" = "UPC_TYPE_INTERNAL" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A13)" + device ref usb2_port10 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A2 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(RIGHT, LEFT, ACPI_PLD_GROUP(4, 1))" + device ref usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A0 (MLB)"" + register "type" = "UPC_TYPE_USB3_A" + register "use_custom_pld" = "true" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, LEFT, ACPI_PLD_GROUP(3, 1))" + device ref usb3_port3 on end + end + end + end + end + device ref pcie4_1 on + # Enable CPU PCIE RP 3 using CLK 0 + register "cpu_pcie_rp[CPU_RP(3)]" = "{ + .clk_req = 0, + .clk_src = 0, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + .pcie_rp_aspm = ASPM_L1, + }" + probe STORAGE STORAGE_NVME + probe unprovisioned + end + device ref pcie_rp4 on + # Enable WWAN PCIE 4 using clk 6 + register "pch_pcie_rp[PCH_RP(4)]" = "{ + .clk_src = 6, + .clk_req = 6, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "6" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + register "use_rp_mutex" = "true" + device generic 0 alias rp4_rtd3 on + probe DB_USB DB_1A_LTE + end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)" + register "wake_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPP_E5)" + register "add_acpi_dma_property" = "true" + use rp4_rtd3 as rtd3dev + device generic 0 alias rp4_wwan on + probe DB_USB DB_1A_LTE + end + end + probe DB_USB DB_1A_LTE + end + device ref pcie_rp7 on + register "pch_pcie_rp[PCH_RP(7)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/wifi/generic + register "wake" = "GPE0_DW0_03" #GPP_B3 + register "add_acpi_dma_property" = "true" + use usb2_port10 as bluetooth_companion + device pci 00.0 on + probe WIFI_BT WIFI_BT_PCIE + probe unprovisioned + end + end + chip soc/intel/common/block/pcie/rtd3 + # enable_gpio is controlled by the EC with EC_EN_PP3300_WLAN + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H2)" + register "srcclk_pin" = "1" + device generic 0 on end + end + probe WIFI_BT WIFI_BT_PCIE + probe unprovisioned + end + device ref pcie_rp8 on + # Enable PCIE 8 using clk 2 + register "pch_pcie_rp[PCH_RP(8)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip drivers/net + register "customized_leds" = "0x05af" + register "device_index" = "0" + register "enable_aspm_l1_2" = "1" + register "add_acpi_dma_property" = "true" + device pci 00.0 on end + end + end #RTL8111H Ethernet NIC + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "add_acpi_dma_property" = "true" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + probe WIFI_BT WIFI_BT_CNVI + probe unprovisioned + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 alias ish_conf on end + end + probe STORAGE STORAGE_UFS + probe unprovisioned + end + device ref ufs on + probe STORAGE STORAGE_UFS + probe unprovisioned + end + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E3_IRQ)" + register "wake" = "GPE0_DW2_03" #GPP_E3 + register "detect" = "1" + device i2c 15 on end + end + end #I2C0 + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN2513"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" + register "generic.reset_delay_ms" = "150" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe PANEL TOUCH_ELAN_HID_I2C + probe unprovisioned + end + end + chip drivers/i2c/hid + register "generic.hid" = ""GTCH7503"" + register "generic.desc" = ""G2TOUCH Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F18_IRQ)" + register "generic.detect" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F17)" + register "generic.reset_delay_ms" = "150" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F7)" + register "generic.enable_delay_ms" = "6" + register "generic.has_power_resource" = "1" + register "generic.use_gpio_for_status" = "true" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on + probe PANEL TOUCH_G2TOUCH_HID_I2C + end + end + end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E4_IRQ)" + register "wake" = "GPE0_DW2_04" #GPP_E4 + register "has_power_resource" = "true" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D9)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D11)" + register "enable_delay_ms" = "3" + device spi 0 on + probe FP FP_PRESENT + probe unprovisioned + end + end # FPMCU + end + end +end diff --git a/src/mainboard/google/brox/variants/caboc/ramstage.c b/src/mainboard/google/brox/variants/caboc/ramstage.c new file mode 100644 index 0000000000..5af6d57247 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/ramstage.c @@ -0,0 +1,43 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include +#include +#include +#include + +/* + * SKU_ID, TDP (Watts), pl1_min (milliWatts), pl1_max (milliWatts), + * pl2_min (milliWatts), pl2_max (milliWatts), pl4 (milliWatts) + * Following values are for performance config as per document #640982 + */ + +const struct cpu_power_limits performance_efficient_limits[] = { + { + .mchid = PCI_DID_INTEL_RPL_P_ID_3, + .cpu_tdp = 15, + .pl1_min_power = 15000, + .pl1_max_power = 15000, + .pl2_min_power = 55000, + .pl2_max_power = 55000, + .pl4_power = 114000 + }, + { + .mchid = PCI_DID_INTEL_RPL_P_ID_4, + .cpu_tdp = 15, + .pl1_min_power = 15000, + .pl1_max_power = 15000, + .pl2_min_power = 55000, + .pl2_max_power = 55000, + .pl4_power = 114000 + }, +}; + +void __weak variant_devtree_update(void) +{ + printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__); + + const struct cpu_power_limits *limits = performance_efficient_limits; + size_t limits_size = ARRAY_SIZE(performance_efficient_limits); + + variant_update_power_limits(limits, limits_size); +} diff --git a/src/mainboard/google/brox/variants/caboc/variant.c b/src/mainboard/google/brox/variants/caboc/variant.c new file mode 100644 index 0000000000..666e370008 --- /dev/null +++ b/src/mainboard/google/brox/variants/caboc/variant.c @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + if (fw_config_probe(FW_CONFIG(WIFI_BT, WIFI_BT_CNVI)) || (!fw_config_is_provisioned())) { + printk(BIOS_INFO, "CNVi bluetooth enabled by fw_config\n"); + config->cnvi_bt_core = true; + } +} + +const char *get_wifi_sar_cbfs_filename(void) +{ + return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); +} + +const char *variant_get_auxfw_version_file(void) +{ + return NULL; +}