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UPSTREAM: nb/intel/sandybridge/raminit: Advertise correct frequency

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As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the
reference clock can be 100Mhz.

Decode the register and use the reference clock to calculate
the selected DDR frequency.

Tested on Lenovo T430.

BUG=none
BRANCH=none
TEST=none

Change-Id: Ia5f46992e4d536a21922721eb97061a78e067e74
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6ab7e5e090
Original-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4
Original-Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Original-Reviewed-on: https://review.coreboot.org/19995
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://chromium-review.googlesource.com/528271
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Patrick Rudolph 2017-05-31 18:21:59 +02:00 • committed by chrome-bot
commit ce45980ecd
1 changed files with 5 additions and 2 deletions
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7
src/northbridge/intel/sandybridge/raminit.c
View file

@ -123,14 +123,17 @@ static void fill_smbios17(ramctr_timing *ctrl)
static void report_memory_config(void)
{
u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS];
int i;
int i, refclk;
addr_decoder_common = MCHBAR32(0x5000);
addr_decode_ch[0] = MCHBAR32(0x5004);
addr_decode_ch[1] = MCHBAR32(0x5008);
refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133;
printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk);
printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n",
(MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100);
(MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100);
printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n",
addr_decoder_common & 3, (addr_decoder_common >> 2) & 3,
(addr_decoder_common >> 4) & 3);