From ce3b7f0e34257ea20a5694b2180d6f7bcf321079 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 25 Oct 2024 17:06:21 -0700 Subject: [PATCH] soc/intel/pantherlake: Inject CSE TS into CBMEM timestamp table Get boot performance timestamps from CSE and inject them into CBMEM timestamp table. For Panther Lake, remove "Die Management Unit (DMU) load completed" and add "ESE completed AUnit loading" instead. 990:CSME ROM started execution 0 992:ESE completed AUnit loading 0 944:CSE sent 'Boot Stall Done' to PMC 174,000 945:CSE started to handle ICC configuration 274,000 (100,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 274,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 448,000 (174,000) 0:1st timestamp 556,874 (108,874) BUG=b:376218080 TEST=Able to see TS elapse prior to IA reset on Fatcat Signed-off-by: Bora Guvendik Change-Id: Ie7716b8c371b82c13da1b0217dce1a16e7b95cee Reviewed-on: https://review.coreboot.org/c/coreboot/+/84872 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/common/block/cse/Kconfig | 7 ++++ .../block/include/intelblocks/cse_telemetry.h | 2 + .../include/intelblocks/cse_telemetry_v3.h | 41 +++++++++++++++++++ src/soc/intel/pantherlake/cse_telemetry.c | 4 +- 4 files changed, 52 insertions(+), 2 deletions(-) create mode 100644 src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index bfef3d5db8..d1548a1fcb 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -295,6 +295,13 @@ config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2 This config will make mainboard use version 2 of the CSE timestamp definitions, it can be used for Meteor Lake M/P. +config SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3 + bool + select SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY + help + This config will make mainboard use version 3 of the CSE timestamp + definitions, it can be used for Panther Lake U/H. + config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool default !SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h index 291a264725..66cc7f40db 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry.h @@ -7,6 +7,8 @@ #include "cse_telemetry_v1.h" #elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2) #include "cse_telemetry_v2.h" +#elif CONFIG(SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V3) +#include "cse_telemetry_v3.h" #endif #endif // SOC_INTEL_COMMON_CSE_TELEMETRY_H diff --git a/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h new file mode 100644 index 0000000000..6dbadff986 --- /dev/null +++ b/src/soc/intel/common/block/include/intelblocks/cse_telemetry_v3.h @@ -0,0 +1,41 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H +#define SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H + +enum cse_boot_perf_data_v3 { + /* CSME ROM start execution */ + PERF_DATA_CSME_ROM_START = 0, + + /* 1 - 5 Reserved */ + + /* CSME RBE set "Boot Stall Done" indication to PMC */ + PERF_DATA_CSME_RBE_BOOT_STALL_DONE_TO_PMC = 6, + + /* 7 - 14 Reserved */ + + /* CSME got ICC_CFG_START message from PMC */ + PERF_DATA_CSME_GOT_ICC_CFG_START_MSG_FROM_PMC = 15, + + /* 15 - 16 Reserved */ + + /* CSME set "Host Boot Prep Done" indication to PMC */ + PERF_DATA_CSME_HOST_BOOT_PREP_DONE = 17, + + /* 18 - 32 Reserved */ + + /* PMC sent "Core Reset Done Ack - Sent" message to CSME */ + PERF_DATA_PMC_SENT_CRDA = 33, + + /* 34 - 35 Reserved */ + + /* ESE completed AUnit loading */ + PERF_DATA_ESE_LOAD_AUNIT_COMPLETED = 36, + + /* 37 - 62 Reserved */ + + /* Timestamp when CSME responded to BupGetBootData message itself */ + PERF_DATA_CSME_GET_PERF_RESPONSE = 63, +}; + +#endif /* SOC_INTEL_COMMON_CSE_TELEMETRY_V3_H */ diff --git a/src/soc/intel/pantherlake/cse_telemetry.c b/src/soc/intel/pantherlake/cse_telemetry.c index 6a599c9306..60faeb2b31 100644 --- a/src/soc/intel/pantherlake/cse_telemetry.c +++ b/src/soc/intel/pantherlake/cse_telemetry.c @@ -24,6 +24,6 @@ void soc_cbmem_inject_telemetry_data(s64 *ts, s64 current_time) start_stamp + ts[PERF_DATA_CSME_HOST_BOOT_PREP_DONE]); timestamp_add(TS_ME_RECEIVED_CRDA_FROM_PMC, start_stamp + ts[PERF_DATA_PMC_SENT_CRDA]); - timestamp_add(TS_ISSE_DMU_LOAD_END, - start_stamp + ts[PERF_DATA_ISSE_DMU_LOAD_COMPLETED]); + timestamp_add(TS_ESE_LOAD_AUNIT_END, + start_stamp + ts[PERF_DATA_ESE_LOAD_AUNIT_COMPLETED]); }