erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

UPSTREAM: google/fizz: Enable SATA on port 1

Browse source 
BUG=b:37486021
BRANCH=None
TEST=compile coreboot and make sure sda and sdb show
     up in /sys/class/block.

Change-Id: I6f88729368ec87c3ff9ee1de4254073a46078c45
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8365aa283
Original-Change-Id: I11344a4a5fc7e5b5d907d25439f92744a5fb70da
Original-Signed-off-by: Shelley Chen <shchen@chromium.org>
Original-Reviewed-on: https://review.coreboot.org/19450
Original-Tested-by: build bot (Jenkins)
Original-Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/490068
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
This commit is contained in:
Shelley Chen 2017-04-24 13:11:43 -07:00 • committed by chrome-bot
commit cd9a18c1a6
1 changed files with 1 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

1
src/mainboard/google/fizz/devicetree.cb
View file

@ -28,6 +28,7 @@ chip soc/intel/skylake
register "SataSalpSupport" = "1"
register "SataMode" = "1"
register "SataPortsEnable[0]" = "1"
register "SataPortsEnable[1]" = "1"
register "EnableAzalia" = "1"
register "DspEnable" = "1"
register "IoBufferOwnership" = "3"