mb/google/ocelot/var/ocelot: Update DDR5 memory configs

This change updates memory configuration for DDR5 boards based
on board ID.
1. Set SaGv frequencies
2. Configure gear settings
3. Map Channel/PHY clock

TEST: Build ocelot image and boot board with DDR5 memory config.

Change-Id: Iffff1f1ac9b886f58304c002defbc008d3c6bbb8
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/89519
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/ocelot/variants/baseboard/include/baseboard/variants.h

@@ -10,6 +10,8 @@
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
+#define BOARD_ID_MASK   0x3f
+
 /* The next set of functions return the gpio table and fill in the number of entries for
  * each table.
  */

src/mainboard/google/ocelot/variants/ocelot/memory.c

@@ -5,7 +5,6 @@
 #include <soc/meminit.h>
 #include <soc/romstage.h>
 
-#define BOARD_ID_MASK	0x3f
 #define SMBUS_ADDR_DIMM	0x50
 
 static const struct mb_cfg lp5_mem_config = {
@@ -56,6 +55,10 @@ static const struct mb_cfg ddr5_mem_config = {
 	.ddr_config = {
 		.dq_pins_interleaved = false,
 	},
+
+	.rcomp = {
+		.resistor = 100,
+	},
 };
 
 const struct mb_cfg *variant_memory_params(void)
@@ -78,7 +81,6 @@ const struct mb_cfg *variant_memory_params(void)
 void variant_get_spd_info(struct mem_spd *spd_info)
 {
 	uint32_t id = board_id() & BOARD_ID_MASK;
-	spd_info->cbfs_index = variant_memory_sku();
 
 	switch (id) {
 	case BOARD_ID_DDR5:
@@ -87,6 +89,7 @@ void variant_get_spd_info(struct mem_spd *spd_info)
 		spd_info->smbus[1].addr_dimm[0] = SMBUS_ADDR_DIMM;
 		break;
 	case BOARD_ID_LP5X:
+		spd_info->cbfs_index = variant_memory_sku();
 		spd_info->topo = MEM_TOPO_MEMORY_DOWN;
 		break;
 	default:

src/mainboard/google/ocelot/variants/ocelot/variant.c

@@ -1,6 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <baseboard/variants.h>
+#include <boardid.h>
 #include <ec/google/chromeec/ec.h>
 #include <fsp/api.h>
 #include <fw_config.h>
@@ -56,6 +57,7 @@ void variant_update_soc_chip_config(struct soc_intel_pantherlake_config *config)
 void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 {
 	FSP_M_CONFIG *m_cfg = &memupd->FspmConfig;
+	uint32_t id = board_id() & BOARD_ID_MASK;
 
 	/* HDA Audio */
 	if (fw_config_probe(FW_CONFIG(AUDIO, AUDIO_ALC256_HDA))) {
@@ -63,6 +65,40 @@ void variant_update_soc_memory_init_params(FSPM_UPD *memupd)
 		m_cfg->PchHdaSdiEnable[0] = true;
 		m_cfg->PchHdaSdiEnable[1] = false;
 	}
+
+	if (id == BOARD_ID_DDR5) {
+		/* Override FSP-M SaGv frequency and gear for DDR5 boards */
+		m_cfg->SaGvFreq[0] = 3200;
+		m_cfg->SaGvGear[0] = GEAR_4;
+
+		m_cfg->SaGvFreq[1] = 4800;
+		m_cfg->SaGvGear[1] = GEAR_4;
+
+		m_cfg->SaGvFreq[2] = 5600;
+		m_cfg->SaGvGear[2] = GEAR_4;
+
+		m_cfg->SaGvFreq[3] = 6400;
+		m_cfg->SaGvGear[3] = GEAR_4;
+
+		/*
+		 * Override FSP-M ChannelToCkdQckMapping to map memory channels
+		 * to Clock Driver (CKD) and Query Clock (QCK) signals.
+		 */
+
+		const uint8_t channel_to_ckd_qck[] = { 1, 0, 0, 0,
+			0, 0, 0, 0 };
+		memcpy(m_cfg->ChannelToCkdQckMapping, channel_to_ckd_qck
+			, sizeof(channel_to_ckd_qck));
+
+		/*
+		 * Override FSP-M PhyClockToCkdDimm to map PHY clocks
+		 * to Clock Driver DIMM connections.
+		 */
+		const uint8_t phy_clock_to_ckd_dimm[] = { 4, 0, 4, 0,
+			0, 0, 0, 0 };
+		memcpy(m_cfg->PhyClockToCkdDimm, phy_clock_to_ckd_dimm,
+			sizeof(phy_clock_to_ckd_dimm));
+	}
 }
 
 bool variant_is_barrel_charger_present(void)