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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner 2019-03-05 16:53:33 -08:00 • committed by Patrick Georgi
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
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4
src/ec/google/chromeec/acpi/ec.asl
View file

@ -94,7 +94,7 @@ Device (EC0)
USPP, 8, // USB Port Power
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
OperationRegion (EMEM, EmbeddedControl,
EC_ACPI_MEM_MAPPED_BEGIN, EC_ACPI_MEM_MAPPED_SIZE)
Field (EMEM, ByteAcc, Lock, Preserve)
@ -525,7 +525,7 @@ Device (EC0)
}
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_USB_PORT_POWER)
/*
* Enable USB Port Power
* Arg0 = USB port ID

6
src/ec/google/chromeec/ec.c
View file

@ -413,7 +413,7 @@ static void google_chromeec_log_device_events(uint64_t mask)
uint64_t events;
int i;
if (!IS_ENABLED(CONFIG_ELOG) || !mask)
if (!CONFIG(ELOG) || !mask)
return;
if (google_chromeec_check_feature(EC_FEATURE_DEVICE_EVENT) != 1)
@ -434,7 +434,7 @@ void google_chromeec_log_events(uint64_t mask)
uint64_t wake_mask;
bool restore_wake_mask = false;
if (!IS_ENABLED(CONFIG_ELOG))
if (!CONFIG(ELOG))
return;
/*
@ -536,7 +536,7 @@ int google_chromeec_set_sku_id(u32 skuid)
return 0;
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_RTC)
#if CONFIG(EC_GOOGLE_CHROMEEC_RTC)
int rtc_get(struct rtc_time *time)
{
struct chromeec_command cmd;

2
src/ec/google/chromeec/ec_i2c.c
View file

@ -22,7 +22,7 @@
#include "ec.h"
#include "ec_commands.h"
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_I2C_PROTO3)
#if CONFIG(EC_GOOGLE_CHROMEEC_I2C_PROTO3)
#define PROTO3_FRAMING_BYTES sizeof(uint32_t)
/* Just use the LPC host packet size to size the buffer. */

10
src/ec/google/chromeec/ec_lpc.c
View file

@ -38,7 +38,7 @@ static void read_bytes(u16 port, unsigned int length, u8 *dest, u8 *csum)
{
int i;
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)
#if CONFIG(EC_GOOGLE_CHROMEEC_MEC)
/* Access desired range though EMI interface */
if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
u8 ret = mec_io_bytes(MEC_IO_READ, MEC_EMI_BASE,
@ -77,7 +77,7 @@ static void write_bytes(u16 port, unsigned int length, u8 *msg, u8 *csum)
{
int i;
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)
#if CONFIG(EC_GOOGLE_CHROMEEC_MEC)
/* Access desired range though EMI interface */
if (port >= MEC_EMI_RANGE_START && port <= MEC_EMI_RANGE_END) {
u8 ret = mec_io_bytes(MEC_IO_WRITE, MEC_EMI_BASE,
@ -132,7 +132,7 @@ static int google_chromeec_wait_ready(u16 port)
EC_LPC_CMDR_BUSY, 0);
}
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
/* Read memmap data through ACPI port 66/62 */
static int read_memmap(u8 *data, u8 offset)
{
@ -166,7 +166,7 @@ static int google_chromeec_command_version(void)
{
u8 id1, id2, flags;
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
#if CONFIG(EC_GOOGLE_CHROMEEC_ACPI_MEMMAP)
if (read_memmap(&id1, EC_MEMMAP_ID) ||
read_memmap(&id2, EC_MEMMAP_ID + 1) ||
read_memmap(&flags, EC_MEMMAP_HOST_CMD_FLAGS)) {
@ -386,7 +386,7 @@ void google_chromeec_ioport_range(uint16_t *out_base, size_t *out_size)
uint16_t base;
size_t size;
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_MEC)) {
if (CONFIG(EC_GOOGLE_CHROMEEC_MEC)) {
base = MEC_EMI_BASE;
size = MEC_EMI_SIZE;
} else {

2
src/ec/google/chromeec/smihandler.c
View file

@ -26,7 +26,7 @@ static int chromeec_process_one_event(void)
uint8_t event = google_chromeec_get_event();
/* Log this event */
if (IS_ENABLED(CONFIG_ELOG_GSMI) && event)
if (CONFIG(ELOG_GSMI) && event)
elog_add_event_byte(ELOG_TYPE_EC_EVENT, event);
switch (event) {

6
src/ec/google/chromeec/switches.c
View file

@ -17,10 +17,10 @@
#include <cbmem.h>
#include <ec/google/chromeec/ec.h>
#if IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC)
#if CONFIG(EC_GOOGLE_CHROMEEC_LPC)
int get_lid_switch(void)
{
if (!IS_ENABLED(CONFIG_VBOOT_LID_SWITCH))
if (!CONFIG(VBOOT_LID_SWITCH))
return -1;
return !!(google_chromeec_get_switches() & EC_SWITCH_LID_OPEN);
@ -30,7 +30,7 @@ int get_lid_switch(void)
int get_recovery_mode_switch(void)
{
/* Check for dedicated recovery switch first. */
if (IS_ENABLED(CONFIG_EC_GOOGLE_CHROMEEC_LPC) &&
if (CONFIG(EC_GOOGLE_CHROMEEC_LPC) &&
(google_chromeec_get_switches() & EC_SWITCH_DEDICATED_RECOVERY))
return 1;

2
src/ec/google/wilco/acpi/superio.asl
View file

@ -29,7 +29,7 @@ Device (SIO)
Method (_STA, 0, NotSerialized)
{
#if IS_ENABLED(CONFIG_DRIVERS_UART_8250IO)
#if CONFIG(DRIVERS_UART_8250IO)
Return (0x0f)
#else
Return (Zero)

2
src/ec/google/wilco/bootblock.c
View file

@ -48,6 +48,6 @@ static void wilco_ec_serial_init(void)
void wilco_ec_early_init(void)
{
if (IS_ENABLED(CONFIG_DRIVERS_UART_8250IO))
if (CONFIG(DRIVERS_UART_8250IO))
wilco_ec_serial_init();
}