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coreboot: Replace all IS_ENABLED(CONFIG_XXX) with CONFIG(XXX)

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This patch is a raw application of

 find src/ -type f | xargs sed -i -e 's/IS_ENABLED\s*(CONFIG_/CONFIG(/g'

Change-Id: I6262d6d5c23cabe23c242b4f38d446b74fe16b88
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Julius Werner 2019-03-05 16:53:33 -08:00 • committed by Patrick Georgi
commit cd49cce7b7
920 changed files with 2285 additions and 2285 deletions
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2
src/drivers/intel/fsp1_0/cache_as_ram.inc
View file

@ -95,7 +95,7 @@ before_romstage:
jmp .Lhlt
.Lhlt:
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#endif
hlt

2
src/drivers/intel/fsp1_0/fastboot_cache.c
View file

@ -57,7 +57,7 @@ static u32 get_mrc_cache_region(struct mrc_data_container **mrc_region_ptr)
{
size_t region_size;
if (IS_ENABLED(CONFIG_MRC_CACHE_FMAP)) {
if (CONFIG(MRC_CACHE_FMAP)) {
struct region_device rdev;
if (fmap_locate_area_as_rdev("RW_MRC_CACHE", &rdev) == 0) {
*mrc_region_ptr = rdev_mmap_full(&rdev);

10
src/drivers/intel/fsp1_0/fsp_util.c
View file

@ -72,19 +72,19 @@ void __noreturn fsp_early_init (FSP_INFO_HEADER *fsp_ptr)
FSP_FSP_INIT FspInitApi;
FSP_INIT_PARAMS FspInitParams;
FSP_INIT_RT_BUFFER FspRtBuffer;
#if IS_ENABLED(CONFIG_FSP_USES_UPD)
#if CONFIG(FSP_USES_UPD)
UPD_DATA_REGION fsp_upd_data;
#endif
/* Load microcode before RAM init */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
memset((void *)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER));
FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP;
FspInitParams.NvsBufferPtr = NULL;
#if IS_ENABLED(CONFIG_FSP_USES_UPD)
#if CONFIG(FSP_USES_UPD)
FspRtBuffer.Common.UpdDataRgnPtr = &fsp_upd_data;
#endif
FspInitParams.RtBufferPtr = (FSP_INIT_RT_BUFFER *)&FspRtBuffer;
@ -238,7 +238,7 @@ void print_fsp_info(void) {
}
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
#if CONFIG(ENABLE_MRC_CACHE)
/**
* Save the FSP memory HOB (mrc data) to the MRC area in CBMEM
*/
@ -308,7 +308,7 @@ static void find_fsp_hob_update_mrc(void *unused)
/* 0x0000: Print all types */
print_hob_type_structure(0x000, FspHobListPtr);
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
#if CONFIG(ENABLE_MRC_CACHE)
if (save_mrc_data(FspHobListPtr))
update_mrc_cache(NULL);
else

4
src/drivers/intel/fsp1_0/fsp_util.h
View file

@ -19,7 +19,7 @@
#include <chipset_fsp_util.h>
#include "fsp_values.h"
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
#if CONFIG(ENABLE_MRC_CACHE)
int save_mrc_data(void *hob_start);
void *find_and_set_fastboot_cache(void);
#endif
@ -61,7 +61,7 @@ void printguid(EFI_GUID *guid);
#define EFI_HOB_TYPE_HANDOFF 0x0001
#define EFI_HOB_TYPE_MEMORY_POOL 0x0007
#if IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)
#if CONFIG(ENABLE_MRC_CACHE)
#define MRC_DATA_ALIGN 0x1000
#define MRC_DATA_SIGNATURE (('M'<<0)|('R'<<8)|('C'<<16)|('D'<<24))

6
src/drivers/intel/fsp1_1/after_raminit.S
View file

@ -30,7 +30,7 @@
/* Switch to the stack in RAM */
movl %eax, %esp
#if IS_ENABLED(CONFIG_SKIP_FSP_CAR)
#if CONFIG(SKIP_FSP_CAR)
/* chipset_teardown_car() is expected to disable cache-as-ram. */
call chipset_teardown_car
@ -87,7 +87,7 @@
* +0: Number of variable MTRRs to clear
*/
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
#if CONFIG(SOC_SETS_MSRS)
push %esp
call soc_set_mtrrs
@ -147,7 +147,7 @@
post_code(0x3a)
#if IS_ENABLED(CONFIG_SOC_SETS_MSRS)
#if CONFIG(SOC_SETS_MSRS)
call soc_enable_mtrrs
#else
/* Enable MTRR. */

2
src/drivers/intel/fsp1_1/cache_as_ram.inc
View file

@ -189,7 +189,7 @@ halt2:
.Lhlt:
xchg %al, %ah
#if IS_ENABLED(CONFIG_POST_IO)
#if CONFIG(POST_IO)
outb %al, $CONFIG_POST_IO_PORT
#else
post_code(POST_DEAD_CODE)

2
src/drivers/intel/fsp1_1/fsp_util.c
View file

@ -102,7 +102,7 @@ void print_fsp_info(FSP_INFO_HEADER *fsp_header)
(u8)((fsp_header->ImageRevision >> 16) & 0xff),
(u8)((fsp_header->ImageRevision >> 8) & 0xff),
(u8)(fsp_header->ImageRevision & 0xff));
#if IS_ENABLED(CONFIG_DISPLAY_FSP_ENTRY_POINTS)
#if CONFIG(DISPLAY_FSP_ENTRY_POINTS)
printk(BIOS_SPEW, "FSP Entry Points:\n");
printk(BIOS_SPEW, " 0x%p: Image Base\n", fsp_base);
printk(BIOS_SPEW, " 0x%p: TempRamInit\n",

14
src/drivers/intel/fsp1_1/raminit.c
View file

@ -51,7 +51,7 @@ void raminit(struct romstage_params *params)
VPD_DATA_REGION *vpd_ptr;
UPD_DATA_REGION *upd_ptr;
int fsp_verification_failure = 0;
#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
#if CONFIG(DISPLAY_HOBS)
unsigned long int data;
EFI_PEI_HOB_POINTERS hob_ptr;
#endif
@ -101,13 +101,13 @@ void raminit(struct romstage_params *params)
soc_memory_init_params(params, &memory_init_params);
mainboard_memory_init_params(params, &memory_init_params);
if (IS_ENABLED(CONFIG_MMA))
if (CONFIG(MMA))
setup_mma(&memory_init_params);
post_code(POST_MEM_PREINIT_PREP_END);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
if (CONFIG(DISPLAY_UPD_DATA))
soc_display_memory_init_params(original_params,
&memory_init_params);
@ -146,7 +146,7 @@ void raminit(struct romstage_params *params)
}
/* Display SMM area */
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
#if CONFIG(HAVE_SMI_HANDLER)
char *smm_base;
size_t smm_size;
@ -162,7 +162,7 @@ void raminit(struct romstage_params *params)
fsp_reserved_bytes);
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
fsp_reserved_bytes)) {
#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
#if CONFIG(HAVE_ACPI_RESUME)
printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
/* FIXME: A "system" reset is likely enough: */
@ -194,7 +194,7 @@ void raminit(struct romstage_params *params)
memory_info_hob);
}
#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
#if CONFIG(DISPLAY_HOBS)
if (hob_list_ptr == NULL)
die("ERROR - HOB pointer is NULL!\n");
@ -266,7 +266,7 @@ void raminit(struct romstage_params *params)
(unsigned int)fsp_reserved_memory_area))) {
fsp_verification_failure = 1;
printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
#if CONFIG(HAVE_SMI_HANDLER)
if (cbmem_root != NULL) {
size_t delta_bytes = (unsigned int)smm_base
- cbmem_root->PhysicalStart

14
src/drivers/intel/fsp1_1/ramstage.c
View file

@ -55,7 +55,7 @@ static void display_hob_info(FSP_INFO_HEADER *fsp_info_header)
int missing_hob = 0;
void *hob_list_ptr = get_hob_list();
if (!IS_ENABLED(CONFIG_DISPLAY_HOBS))
if (!CONFIG(DISPLAY_HOBS))
return;
/* Verify the HOBs */
@ -117,12 +117,12 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
soc_silicon_init_params(&silicon_init_params);
/* Locate VBT and pass to FSP GOP */
if (IS_ENABLED(CONFIG_RUN_FSP_GOP))
if (CONFIG(RUN_FSP_GOP))
load_vbt(is_s3_wakeup, &silicon_init_params);
mainboard_silicon_init_params(&silicon_init_params);
/* Display the UPD data */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
if (CONFIG(DISPLAY_UPD_DATA))
soc_display_silicon_init_params(original_params,
&silicon_init_params);
@ -139,7 +139,7 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
printk(BIOS_DEBUG, "FspSiliconInit returned 0x%08x\n", status);
/* Mark graphics init done after SiliconInit if VBT was provided */
#if IS_ENABLED(CONFIG_RUN_FSP_GOP)
#if CONFIG(RUN_FSP_GOP)
/* GraphicsConfigPtr doesn't exist in Quark X1000's FSP, so this needs
* to be #if'd out instead of using if (). */
if (silicon_init_params.GraphicsConfigPtr)
@ -152,10 +152,10 @@ void fsp_run_silicon_init(FSP_INFO_HEADER *fsp_info_header, int is_s3_wakeup)
static void fsp_cache_save(struct prog *fsp)
{
if (IS_ENABLED(CONFIG_DISPLAY_SMM_MEMORY_MAP))
if (CONFIG(DISPLAY_SMM_MEMORY_MAP))
smm_memory_map();
if (IS_ENABLED(CONFIG_NO_STAGE_CACHE))
if (CONFIG(NO_STAGE_CACHE))
return;
printk(BIOS_DEBUG, "FSP: Saving binary in cache\n");
@ -192,7 +192,7 @@ void fsp_load(void)
if (load_done)
return;
if (is_s3_wakeup && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
if (is_s3_wakeup && !CONFIG(NO_STAGE_CACHE)) {
printk(BIOS_DEBUG, "FSP: Loading binary from cache\n");
stage_cache_load_stage(STAGE_REFCODE, &fsp);
} else {

14
src/drivers/intel/fsp1_1/romstage.c
View file

@ -52,13 +52,13 @@ asmlinkage void *romstage_main(FSP_INFO_HEADER *fih)
timestamp_add_now(TS_START_ROMSTAGE);
/* Load microcode before RAM init */
if (IS_ENABLED(CONFIG_SUPPORT_CPU_UCODE_IN_CBFS))
if (CONFIG(SUPPORT_CPU_UCODE_IN_CBFS))
intel_update_microcode_from_cbfs();
memset(&pei_data, 0, sizeof(pei_data));
/* Display parameters */
if (!IS_ENABLED(CONFIG_NO_MMCONF_SUPPORT))
if (!CONFIG(NO_MMCONF_SUPPORT))
printk(BIOS_SPEW, "CONFIG_MMCONF_BASE_ADDRESS: 0x%08x\n",
CONFIG_MMCONF_BASE_ADDRESS);
printk(BIOS_INFO, "Using FSP 1.1\n");
@ -104,7 +104,7 @@ void romstage_common(struct romstage_params *params)
pei_data->boot_mode = params->power_state->prev_sleep_state;
s3wake = params->power_state->prev_sleep_state == ACPI_S3;
if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake)
if (CONFIG(ELOG_BOOT_COUNT) && !s3wake)
boot_count_increment();
/* Perform remaining SOC initialization */
@ -119,7 +119,7 @@ void romstage_common(struct romstage_params *params)
/* Recovery mode does not use MRC cache */
printk(BIOS_DEBUG,
"Recovery mode: not using MRC cache.\n");
} else if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)
} else if (CONFIG(CACHE_MRC_SETTINGS)
&& (!mrc_cache_get_current(MRC_TRAINING_DATA,
params->fsp_version,
&rdev))) {
@ -128,7 +128,7 @@ void romstage_common(struct romstage_params *params)
region_device_sz(&rdev);
params->pei_data->saved_data = rdev_mmap_full(&rdev);
/* Assume boot device is memory mapped. */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
} else if (params->pei_data->boot_mode == ACPI_S3) {
/* Waking from S3 and no cache. */
printk(BIOS_DEBUG,
@ -146,7 +146,7 @@ void romstage_common(struct romstage_params *params)
timestamp_add_now(TS_AFTER_INITRAM);
/* Save MRC output */
if (IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS)) {
if (CONFIG(CACHE_MRC_SETTINGS)) {
printk(BIOS_DEBUG, "MRC data at %p %d bytes\n",
pei_data->data_to_save, pei_data->data_to_save_size);
if ((params->pei_data->boot_mode != ACPI_S3)
@ -214,7 +214,7 @@ __weak void mainboard_save_dimm_info(
memory_info_hob = (FSP_SMBIOS_MEMORY_INFO *)(hob_ptr + 1);
/* Display the data in the FSP_SMBIOS_MEMORY_INFO HOB */
if (IS_ENABLED(CONFIG_DISPLAY_HOBS)) {
if (CONFIG(DISPLAY_HOBS)) {
printk(BIOS_DEBUG, "FSP_SMBIOS_MEMORY_INFO HOB\n");
printk(BIOS_DEBUG, " 0x%02x: Revision\n",
memory_info_hob->Revision);

2
src/drivers/intel/fsp1_1/stack.c
View file

@ -116,7 +116,7 @@ void *setup_stack_and_mtrrs(void)
slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
num_mtrrs++;
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
#if CONFIG(HAVE_SMI_HANDLER)
void *smm_base;
size_t smm_size;
uint32_t tseg_base;

2
src/drivers/intel/fsp1_1/vbt.c
View file

@ -34,7 +34,7 @@ void load_vbt(uint8_t s3_resume, SILICON_INIT_UPD *params)
/* Get VBT data */
vbt_data = locate_vbt(&vbt_len);
if (vbt_data != NULL) {
if (IS_ENABLED(CONFIG_DISPLAY_VBT)) {
if (CONFIG(DISPLAY_VBT)) {
/* Display the vbt file contents */
printk(BIOS_DEBUG, "VBT Data:\n");
hexdump(vbt_data, vbt_len);

24
src/drivers/intel/fsp2_0/debug.c
View file

@ -31,11 +31,11 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
display_mtrrs();
/* Display the UPD values */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
if (CONFIG(DISPLAY_UPD_DATA))
fspm_display_upd_values(fspm_old_upd, fspm_new_upd);
/* Display the call entry point and parameters */
if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
return;
printk(BIOS_SPEW, "Calling FspMemoryInit: 0x%p\n", memory_init);
printk(BIOS_SPEW, "\t0x%p: raminit_upd\n", fspm_new_upd);
@ -44,7 +44,7 @@ void fsp_debug_before_memory_init(fsp_memory_init_fn memory_init,
void fsp_debug_after_memory_init(uint32_t status)
{
if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
printk(BIOS_SPEW, "FspMemoryInit returned 0x%08x\n", status);
if (status != FSP_SUCCESS)
@ -55,9 +55,9 @@ void fsp_debug_after_memory_init(uint32_t status)
die("ERROR - HOB list pointer was not returned!\n");
/* Display and verify the HOBs */
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
if (CONFIG(DISPLAY_HOBS))
fsp_display_hobs();
if (IS_ENABLED(CONFIG_VERIFY_HOBS))
if (CONFIG(VERIFY_HOBS))
fsp_verify_memory_init_hobs();
display_mtrrs();
@ -74,11 +74,11 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
display_mtrrs();
/* Display the UPD values */
if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
if (CONFIG(DISPLAY_UPD_DATA))
soc_display_fsps_upd_params(fsps_old_upd, fsps_new_upd);
/* Display the call to FSP SiliconInit */
if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
return;
printk(BIOS_SPEW, "Calling FspSiliconInit: 0x%p\n", silicon_init);
printk(BIOS_SPEW, "\t0x%p: upd\n", fsps_new_upd);
@ -86,11 +86,11 @@ void fsp_debug_before_silicon_init(fsp_silicon_init_fn silicon_init,
void fsp_debug_after_silicon_init(uint32_t status)
{
if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
printk(BIOS_SPEW, "FspSiliconInit returned 0x%08x\n", status);
/* Display the HOBs */
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
if (CONFIG(DISPLAY_HOBS))
fsp_display_hobs();
display_mtrrs();
@ -104,7 +104,7 @@ void fsp_before_debug_notify(fsp_notify_fn notify,
const struct fsp_notify_params *notify_params)
{
/* Display the call to FspNotify */
if (!IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
if (!CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
return;
printk(BIOS_SPEW, "0x%08x: notify_params->phase\n",
notify_params->phase);
@ -114,11 +114,11 @@ void fsp_before_debug_notify(fsp_notify_fn notify,
void fsp_debug_after_notify(uint32_t status)
{
if (IS_ENABLED(CONFIG_DISPLAY_FSP_CALLS_AND_STATUS))
if (CONFIG(DISPLAY_FSP_CALLS_AND_STATUS))
printk(BIOS_SPEW, "FspNotify returned 0x%08x\n", status);
/* Display the HOBs */
if (IS_ENABLED(CONFIG_DISPLAY_HOBS))
if (CONFIG(DISPLAY_HOBS))
fsp_display_hobs();
display_mtrrs();

2
src/drivers/intel/fsp2_0/hand_off_block.c
View file

@ -219,7 +219,7 @@ const void *fsp_find_extension_hob_by_guid(const uint8_t *guid, size_t *size)
static void display_fsp_version_info_hob(const void *hob, size_t size)
{
#if IS_ENABLED(CONFIG_DISPLAY_FSP_VERSION_INFO)
#if CONFIG(DISPLAY_FSP_VERSION_INFO)
const FIRMWARE_VERSION_INFO *fvi;
const FIRMWARE_VERSION_INFO_HOB *fvih =
(FIRMWARE_VERSION_INFO_HOB *)hob;

2
src/drivers/intel/fsp2_0/include/fsp/soc_binding.h
View file

@ -26,7 +26,7 @@
#include <Base.h>
#include <FspmUpd.h>
#include <FspsUpd.h>
#if IS_ENABLED(CONFIG_DISPLAY_FSP_VERSION_INFO)
#if CONFIG(DISPLAY_FSP_VERSION_INFO)
#include <FirmwareVersionInfoHob.h>
#endif

28
src/drivers/intel/fsp2_0/memory_init.c
View file

@ -38,7 +38,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
size_t mrc_data_size;
const void *mrc_data;
if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS) || s3wake)
if (!CONFIG(CACHE_MRC_SETTINGS) || s3wake)
return;
mrc_data = fsp_find_nv_storage_data(&mrc_data_size);
@ -57,7 +57,7 @@ static void save_memory_training_data(bool s3wake, uint32_t fsp_version)
mrc_data_size) < 0)
printk(BIOS_ERR, "Failed to stash MRC data\n");
if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH))
if (CONFIG(FSP2_0_USES_TPM_MRC_HASH))
mrc_cache_update_hash(mrc_data, mrc_data_size);
}
@ -74,7 +74,7 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
range_entry_size(&fsp_mem));
} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
range_entry_size(&fsp_mem))) {
if (IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)) {
if (CONFIG(HAVE_ACPI_RESUME)) {
printk(BIOS_ERR,
"Failed to recover CBMEM in S3 resume.\n");
/* Failed S3 resume, reset to come up cleanly */
@ -97,8 +97,8 @@ static void do_fsp_post_memory_init(bool s3wake, uint32_t fsp_version)
* Initialize the TPM, unless the TPM was already initialized
* in verstage and used to verify romstage.
*/
if ((IS_ENABLED(CONFIG_TPM1) || IS_ENABLED(CONFIG_TPM2)) &&
!IS_ENABLED(CONFIG_VBOOT_STARTS_IN_BOOTBLOCK))
if ((CONFIG(TPM1) || CONFIG(TPM2)) &&
!CONFIG(VBOOT_STARTS_IN_BOOTBLOCK))
tpm_setup(s3wake);
}
@ -109,7 +109,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
arch_upd->NvsBufferPtr = NULL;
if (!IS_ENABLED(CONFIG_CACHE_MRC_SETTINGS))
if (!CONFIG(CACHE_MRC_SETTINGS))
return;
/*
@ -118,7 +118,7 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
* 2. Memory retrain switch is set.
*/
if (vboot_recovery_mode_enabled()) {
if (!IS_ENABLED(CONFIG_HAS_RECOVERY_MRC_CACHE))
if (!CONFIG(HAS_RECOVERY_MRC_CACHE))
return;
if (vboot_recovery_mode_memory_retrain())
return;
@ -128,13 +128,13 @@ static void fsp_fill_mrc_cache(FSPM_ARCH_UPD *arch_upd, uint32_t fsp_version)
return;
/* Assume boot device is memory mapped. */
assert(IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED));
assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
data = rdev_mmap_full(&rdev);
if (data == NULL)
return;
if (IS_ENABLED(CONFIG_FSP2_0_USES_TPM_MRC_HASH) &&
if (CONFIG(FSP2_0_USES_TPM_MRC_HASH) &&
!mrc_cache_verify_hash(data, region_device_sz(&rdev)))
return;
@ -174,7 +174,7 @@ static enum cb_err setup_fsp_stack_frame(FSPM_ARCH_UPD *arch_upd,
* setting up seprate stack frame. FSP 2.1 would not relocate stack
* top and does not reinitialize stack pointer.
*/
if (IS_ENABLED(CONFIG_FSP_USES_CB_STACK)) {
if (CONFIG(FSP_USES_CB_STACK)) {
arch_upd->StackBase = (void *)_car_stack_end;
arch_upd->StackSize = CONFIG_DCACHE_BSP_STACK_SIZE;
return CB_SUCCESS;
@ -254,7 +254,7 @@ static uint32_t fsp_memory_settings_version(const struct fsp_header *hdr)
/* Use the full FSP version by default. */
uint32_t ver = hdr->fsp_revision;
if (!IS_ENABLED(CONFIG_FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS))
if (!CONFIG(FSP_PLATFORM_MEMORY_SETTINGS_VERSIONS))
return ver;
ver &= ~0xff;
@ -298,7 +298,7 @@ static void do_fsp_memory_init(struct fsp_header *hdr, bool s3wake,
/* Give SoC and mainboard a chance to update the UPD */
platform_fsp_memory_init_params_cb(&fspm_upd, fsp_version);
if (IS_ENABLED(CONFIG_MMA))
if (CONFIG(MMA))
setup_mma(&fspm_upd.FspmConfig);
post_code(POST_MEM_PREINIT_PREP_END);
@ -383,7 +383,7 @@ void fsp_memory_init(bool s3wake)
struct memranges memmap;
struct range_entry freeranges[2];
if (IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) && !s3wake)
if (CONFIG(ELOG_BOOT_COUNT) && !s3wake)
boot_count_increment();
if (cbfs_boot_locate(&file_desc, name, NULL)) {
@ -399,7 +399,7 @@ void fsp_memory_init(bool s3wake)
_car_relocatable_data_end - _car_region_start, 0);
memranges_insert(&memmap, (uintptr_t)_program, REGION_SIZE(program), 0);
if (!IS_ENABLED(CONFIG_FSP_M_XIP))
if (!CONFIG(FSP_M_XIP))
status = load_fspm_mem(&hdr, &file_data, &memmap);
else
status = load_fspm_xip(&hdr, &file_data);

2
src/drivers/intel/fsp2_0/silicon_init.c
View file

@ -77,7 +77,7 @@ void fsps_load(bool s3wake)
if (load_done)
return;
if (s3wake && !IS_ENABLED(CONFIG_NO_STAGE_CACHE)) {
if (s3wake && !CONFIG(NO_STAGE_CACHE)) {
printk(BIOS_DEBUG, "Loading FSPS from stage_cache\n");
stage_cache_load_stage(STAGE_REFCODE, &fsps);
if (fsp_validate_component(hdr, prog_rdev(&fsps)) != CB_SUCCESS)

2
src/drivers/intel/fsp2_0/util.c
View file

@ -80,7 +80,7 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr,
rdev_munmap(rdev, membase);
if (IS_ENABLED(CONFIG_DISPLAY_FSP_HEADER))
if (CONFIG(DISPLAY_FSP_HEADER))
fsp_print_header_info(hdr);
/* Check if size specified in the header matches the cbfs file size */

2
src/drivers/intel/gma/int15.h
View file

@ -26,7 +26,7 @@ enum {
};
#if IS_ENABLED(CONFIG_VGA_ROM_RUN)
#if CONFIG(VGA_ROM_RUN)
/* Install custom int15 handler for VGA OPROM */
void install_intel_vga_int15_handler(int active_lfp, int pfit, int display, int panel_type);
#else

2
src/drivers/intel/gma/opregion.c
View file

@ -91,7 +91,7 @@ void intel_gma_opregion_register(uintptr_t opregion)
* Atom-based platforms use a combined SMI/SCI register,
* whereas non-Atom platforms use a separate SCI register.
*/
if (IS_ENABLED(CONFIG_INTEL_GMA_SWSMISCI))
if (CONFIG(INTEL_GMA_SWSMISCI))
sci_reg = SWSMISCI;
else
sci_reg = SWSCI;

2
src/drivers/intel/gma/vbt.c
View file

@ -60,7 +60,7 @@ static size_t generate_vbt(const struct i915_gpu_controller_info *const conf,
genfeat->flexaim = 1;
genfeat->download_ext_vbt = 1;
genfeat->enable_ssc = conf->use_spread_spectrum_clock;
genfeat->ssc_freq = IS_ENABLED(CONFIG_INTEL_GMA_SSC_ALTERNATE_REF);
genfeat->ssc_freq = CONFIG(INTEL_GMA_SSC_ALTERNATE_REF);
genfeat->rsvd10 = 0x4;
genfeat->legacy_monitor_detect = 1;
genfeat->int_crt_support = 1;

16
src/drivers/intel/wifi/wifi.c
View file

@ -32,7 +32,7 @@
#define PMCS_DR 0xcc
#define PME_STS (1 << 15)
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
#if CONFIG(GENERATE_SMBIOS_TABLES)
static int smbios_write_wifi(struct device *dev, int *handle,
unsigned long *current)
{
@ -71,7 +71,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits)
return -1;
}
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
static void emit_sar_acpi_structures(void)
{
int i, j, package_size;
@ -139,7 +139,7 @@ static void emit_sar_acpi_structures(void)
acpigen_pop_len();
if (!IS_ENABLED(CONFIG_GEO_SAR_ENABLE))
if (!CONFIG(GEO_SAR_ENABLE))
return;
/*
@ -219,7 +219,7 @@ static void intel_wifi_fill_ssdt(struct device *dev)
acpigen_write_PRW(config->wake, 3);
/* Fill regulatory domain structure */
if (IS_ENABLED(CONFIG_HAVE_REGULATORY_DOMAIN)) {
if (CONFIG(HAVE_REGULATORY_DOMAIN)) {
/*
* Name ("WRDD", Package () {
* WRDD_REVISION, // Revision
@ -240,7 +240,7 @@ static void intel_wifi_fill_ssdt(struct device *dev)
}
/* Fill Wifi sar related ACPI structures */
if (IS_ENABLED(CONFIG_USE_SAR))
if (CONFIG(USE_SAR))
emit_sar_acpi_structures();
acpigen_pop_len(); /* Device */
@ -260,7 +260,7 @@ static void wifi_pci_dev_init(struct device *dev)
{
pci_dev_init(dev);
if (IS_ENABLED(CONFIG_ELOG)) {
if (CONFIG(ELOG)) {
uint32_t val;
val = pci_read_config16(dev, PMCS_DR);
if (val & PME_STS)
@ -277,11 +277,11 @@ struct device_operations device_ops = {
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = wifi_pci_dev_init,
#if IS_ENABLED(CONFIG_GENERATE_SMBIOS_TABLES)
#if CONFIG(GENERATE_SMBIOS_TABLES)
.get_smbios_data = smbios_write_wifi,
#endif
.ops_pci = &pci_ops,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
#if CONFIG(HAVE_ACPI_TABLES)
.acpi_name = intel_wifi_acpi_name,
.acpi_fill_ssdt_generator = intel_wifi_fill_ssdt,
#endif