diff --git a/src/southbridge/intel/bd82x6x/chip.h b/src/southbridge/intel/bd82x6x/chip.h
index 188595a89b..b4b6ea33e7 100644
--- a/src/southbridge/intel/bd82x6x/chip.h
+++ b/src/southbridge/intel/bd82x6x/chip.h
@@ -72,8 +72,6 @@ struct southbridge_intel_bd82x6x_config {
 	uint32_t xhci_switchable_ports;
 	/* Ports which support SuperSpeed (USB 3.0 additional lanes).  */
 	uint32_t superspeed_capable_ports;
-	/* Overcurrent Mapping for USB 3.0 Ports */
-	uint32_t xhci_overcurrent_mapping;
 
 	uint32_t spi_uvscc;
 	uint32_t spi_lvscc;
diff --git a/util/autoport/bd82x6x.go b/util/autoport/bd82x6x.go
index fefddbcf1d..a94b359b51 100644
--- a/util/autoport/bd82x6x.go
+++ b/util/autoport/bd82x6x.go
@@ -164,7 +164,6 @@ func (b bd82x6x) Scan(ctx Context, addr PCIDevData) {
 	if ok {
 		cur.Registers["xhci_switchable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xd4:0xd8])
 		cur.Registers["superspeed_capable_ports"] = FormatHexLE32(xhciDev.ConfigDump[0xdc:0xe0])
-		cur.Registers["xhci_overcurrent_mapping"] = FormatHexLE32(xhciDev.ConfigDump[0xc0:0xc4])
 	}
 
 	PutPCIChip(addr, cur)