UPSTREAM: Use more secure HTTPS URLs for coreboot sites

The coreboot sites support HTTPS, and requests over HTTP with SSL are
also redirected. So use the more secure URLs, which also saves a
request most of the times, as nothing needs to be redirected.

Run the command below to replace all occurences.

```
$ git grep -l -E 'http://(www.|review.|)coreboot.org'
| xargs sed -i 's,http://\(.*\)coreboot.org,https://\1coreboot.org,g'
```

BUG=none
BRANCH=none
TEST=none

Change-Id: I881e55138a6114c67585ce37d4d719fe2626b83a
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: a8843dee58
Original-Change-Id: If53f8b66f1ac72fb1a38fa392b26eade9963c369
Original-Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Original-Reviewed-on: https://review.coreboot.org/20034
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://chromium-review.googlesource.com/528256
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>

src/cpu/amd/car/cache_as_ram.inc

@@ -378,7 +378,7 @@ fam15_skip_dram_mtrr_setup:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/intel/car/cache_as_ram.inc

@@ -233,7 +233,7 @@ clear_fixed_var_mtrr_out:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/intel/car/cache_as_ram_ht.inc

@@ -306,7 +306,7 @@ no_msr_11e:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/intel/haswell/cache_as_ram.inc

@@ -132,7 +132,7 @@ clear_mtrrs:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/intel/model_2065x/cache_as_ram.inc

@@ -138,7 +138,7 @@ clear_var_mtrrs:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/intel/model_206ax/cache_as_ram.inc

@@ -132,7 +132,7 @@ clear_mtrrs:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/intel/model_6ex/cache_as_ram.inc

@@ -107,7 +107,7 @@ clear_mtrrs:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/cpu/via/car/cache_as_ram.inc

@@ -114,7 +114,7 @@ clear_fixed_var_mtrr_out:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
@@ -160,7 +160,7 @@ clear_fixed_var_mtrr_out:
 #ifdef CARTEST
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %esi
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
@@ -241,7 +241,7 @@ testok:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl	$copy_and_run, %eax
 	andl	$(~(CONFIG_XIP_ROM_SIZE - 1)), %eax

src/drivers/usb/Kconfig

@@ -25,7 +25,7 @@ config USBDEBUG
 	  It also requires a USB2 controller which supports the EHCI
 	  Debug Port capability.
 
-	  See http://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
+	  See https://www.coreboot.org/EHCI_Debug_Port for an up-to-date list
 	  of supported controllers.
 
 	  If unsure, say N.

src/mainboard/supermicro/h8dmr_fam10/README

@@ -17,6 +17,6 @@ while. Again, not an issue specific to this port.
 * to avoid very slow LZMA decompression I use this port with LZMA compression
 disabled in CBFS. I'm not sure what's causing this particular slowness.
 
-See also this thread: http://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
+See also this thread: https://www.coreboot.org/pipermail/coreboot/2009-September/052107.html
 
 Ward, 2009-09-22

src/mainboard/via/epia-m700/romstage.c

@@ -46,7 +46,7 @@
 
 /*
  * This acpi_is_wakeup_early_via_VX800 is from Rudolf's patch on the list:
- * http://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
+ * https://www.coreboot.org/pipermail/coreboot/2008-January/028787.html.
  */
 static int acpi_is_wakeup_early_via_vx800(void)
 {
@@ -527,7 +527,7 @@ void main(unsigned long bist)
 #if PAYLOAD_IS_SEABIOS == 1
 	if (boot_mode == 3) {
 		/* An idea of Libo.Feng at amd.com in
-		 * http://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
+		 * https://www.coreboot.org/pipermail/coreboot/2008-December/043111.html
 		 *
 		 * I want move the 1M data, I have to set some MTRRs myself.
 		 * Setting MTRR before back memory save s3 resume time about

src/northbridge/intel/i82810/raminit.c

@@ -313,7 +313,7 @@ static void set_dram_timing(void)
  * 0x0001   512MB   0xff   256MB dual-sided     256MB dual-sided
  *
  * See also:
- * http://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
+ * https://www.coreboot.org/pipermail/coreboot/2009-May/047966.html
  */
 static void set_dram_buffer_strength(void)
 {

src/soc/intel/broadwell/romstage/cache_as_ram.inc

@@ -134,7 +134,7 @@ clear_mtrrs:
 	xorl	%edx, %edx
 	/*
 	 * IMPORTANT: The following calculation _must_ be done at runtime. See
-	 * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+	 * https://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
 	 */
 	movl    $copy_and_run, %eax
 	andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax