armv7: Change all memory domains to Client so XN bits work

Remember the XN bit? The one we had so much fun with on Nyan (LPAE)
because not setting it allows random instruction prefetches to device
memory that hang the system every few thousand boots? Thankfully, we had
always been setting it in the non-LPAE MMU code already...

"When the XN bit is 1, a Permission fault is generated if the processor
attempts to execute an instruction fetched from the corresponding memory
region. However, when using the Short-descriptor translation table
format, the fault is generated only if the access is to memory in the
Client domain, see Domains[...]" - ARM A.R.M. section B3.7.2

Oops. This patch changes our Domain Access Control Register (DACR) to
set domain 0 (the only one we are using) to Client. This means that
access permissions (AP[2:0] bits) become enforced, but they are already
set to full access (0b011). It also means that non-LPAE systems will not
be allowed to execute from DCACHE_OFF memory with enabled MMU anymore.
As far as I can see, Veyron_Pinky has been the only board that does
that.

BUG=chrome-os-partner:32118
TEST=Booted Veyron_Pinky with MMU in the bootblock, saw hangs that look
like spurious prefetches and confirmed that this patch fixes them.

Change-Id: I30676a5bfe12d516e5f910f51ee6854f6e5be557
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/223783
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/arch/arm/armv7/mmu.c

@@ -302,6 +302,6 @@ void mmu_init(void)
 		0 << 16 | 0 << 0	/* Use TTBR0 for all addresses */
 		);
 
-	/* disable domain-level checking of permissions */
-	write_dacr(~0);
+	/* Set domain 0 to Client so XN bit works (to prevent prefetches) */
+	write_dacr(0x5);
 }