From cbafdf6d005abc49b30d04deb6f40e03a70299ea Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20Kope=C4=87?= Date: Mon, 10 Mar 2025 14:40:38 +0100 Subject: [PATCH] mb/novacustom/mtl-h/ramstage.c: Set Pinmux FSP UPDs MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set Pin Mux FSP UPDs as per mainboard schematic. Change-Id: Id075e236cee64527aab644616186a3e223c1bfc3 Signed-off-by: Michał Kopeć Reviewed-on: https://review.coreboot.org/c/coreboot/+/86788 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/novacustom/mtl-h/ramstage.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/mainboard/novacustom/mtl-h/ramstage.c b/src/mainboard/novacustom/mtl-h/ramstage.c index 19d14a6e1a..637257a016 100644 --- a/src/mainboard/novacustom/mtl-h/ramstage.c +++ b/src/mainboard/novacustom/mtl-h/ramstage.c @@ -35,6 +35,15 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->PchEspiHostC10ReportEnable = 1; // Pinmux configuration + params->PchSerialIoI2cSdaPinMux[3] = 0x1A45CA06; // GPP_H6 + params->PchSerialIoI2cSclPinMux[3] = 0x1A45AA07; // GPP_H7 + + params->PchSerialIoI2cSdaPinMux[4] = 0x8A44CC0C; // GPP_E12 + params->PchSerialIoI2cSclPinMux[4] = 0x8A44AC0D; // GPP_E13 + + params->PchSerialIoI2cSdaPinMux[5] = 0x8A46CE0D; // GPP_F13 + params->PchSerialIoI2cSclPinMux[5] = 0x8A46AE0C; // GPP_F12 + params->CnviRfResetPinMux = 0x194CE404; // GPP_F04 params->CnviClkreqPinMux = 0x394CE605; // GPP_F05