From cb03ba6992a76ce891f1f5fbf8feffb8723578de Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 11 Oct 2013 00:44:06 -0500 Subject: [PATCH] baytrail: fix tsc rate Despite some references to a fixed bclk in some of the docs the bclk is variable per sku. Therefore, perform the calculation according to the BSEL_CR_OVERCLOCK_CONTROL msr which provides the bclk for the cpu cores in Bay Trail. BUG=chrome-os-partner:23166 BRANCH=None TEST=Built and booted B3. correctly says: clocks_per_usec: 2133 Change-Id: I55da45d42e7672fdb3b821c8aed7340a6f73dd08 Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/172771 Reviewed-by: Shawn Nematbakhsh --- src/soc/intel/baytrail/baytrail/msr.h | 1 + src/soc/intel/baytrail/tsc_freq.c | 12 ++++++++++-- 2 files changed, 11 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/baytrail/baytrail/msr.h b/src/soc/intel/baytrail/baytrail/msr.h index 7f3b3b26fd..5094f965c7 100644 --- a/src/soc/intel/baytrail/baytrail/msr.h +++ b/src/soc/intel/baytrail/baytrail/msr.h @@ -21,6 +21,7 @@ #define _BAYTRAIL_MSR_H_ #define MSR_IA32_PLATFORM_ID 0x17 +#define MSR_BSEL_CR_OVERCLOCK_CONTROL 0xcd #define MSR_PLATFORM_INFO 0xce #define MSR_IA32_PERF_CTL 0x199 #define MSR_IA32_MISC_ENABLES 0x1a0 diff --git a/src/soc/intel/baytrail/tsc_freq.c b/src/soc/intel/baytrail/tsc_freq.c index 4622b709d8..3b662fef67 100644 --- a/src/soc/intel/baytrail/tsc_freq.c +++ b/src/soc/intel/baytrail/tsc_freq.c @@ -27,13 +27,21 @@ #include #endif -#define BCLK 100 /* 100 MHz */ unsigned long tsc_freq_mhz(void) { msr_t platform_info; + msr_t clk_info; + unsigned long bclk_khz; platform_info = rdmsr(MSR_PLATFORM_INFO); - return BCLK * ((platform_info.lo >> 8) & 0xff); + clk_info = rdmsr(MSR_BSEL_CR_OVERCLOCK_CONTROL); + switch (clk_info.lo & 0x3) { + case 0: bclk_khz = 83333; break; + case 1: bclk_khz = 100000; break; + case 2: bclk_khz = 133333; break; + case 3: bclk_khz = 116666; break; + } + return (bclk_khz * ((platform_info.lo >> 8) & 0xff)) / 1000; } void set_max_freq(void)