soc/amd: add I3C controller base addresses and devicetree entries

Add the base addresses of the I3C controllers and the mmio devices to
the devicetree for the SoCs that have I3C controllers. The following
documentation was used to verify this:

Mendocino: #57243 Rev 3.08
Rembrandt: #56558 Rev 3.09 (in Mendocino directory)
Phoenix: #57019 Rev 3.09
Glinda: #57254 Rev 3.00
Faegan: #57928 Rev 1.51 (in Glinda directory)

For Genoa, those entries already existed in both its iomap.h and its
devicetree. Cezanne and Picasso don't have I3C controllers.

Change-Id: I6e8073e6498266b909b6cc5f589353f2ed23a62f
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87276
Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/glinda/chipset.cb

@@ -148,4 +148,8 @@ chip soc/amd/glinda
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end

src/soc/amd/glinda/include/soc/iomap.h

@@ -33,6 +33,11 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)

src/soc/amd/mendocino/chipset_mendocino.cb

@@ -93,4 +93,8 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end

src/soc/amd/mendocino/chipset_rembrandt.cb

@@ -96,4 +96,8 @@ chip soc/amd/mendocino
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end

src/soc/amd/mendocino/include/soc/iomap.h

@@ -33,6 +33,11 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)

src/soc/amd/phoenix/chipset_fsp.cb

@@ -145,4 +145,8 @@ chip soc/amd/phoenix
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end

src/soc/amd/phoenix/chipset_opensil.cb

@@ -165,4 +165,8 @@ chip soc/amd/phoenix
 	device mmio 0xfedce000 alias uart_2 off ops amd_uart_mmio_ops end
 	device mmio 0xfedcf000 alias uart_3 off ops amd_uart_mmio_ops end
 	device mmio 0xfedd1000 alias uart_4 off ops amd_uart_mmio_ops end
+	device mmio 0xfedd2000 alias i3c_0 off end
+	device mmio 0xfedd3000 alias i3c_1 off end
+	device mmio 0xfedd4000 alias i3c_2 off end
+	device mmio 0xfedd6000 alias i3c_3 off end
 end

src/soc/amd/phoenix/include/soc/iomap.h

@@ -33,6 +33,11 @@
 #define APU_DMAC4_BASE			0xfedd0000
 #define APU_UART4_BASE			0xfedd1000
 
+#define APU_I3C0_BASE			0xfedd2000
+#define APU_I3C1_BASE			0xfedd3000
+#define APU_I3C2_BASE			0xfedd4000
+#define APU_I3C3_BASE			0xfedd6000
+
 #endif /* ENV_X86 */
 
 #define FLASH_BASE_ADDR			((0xffffffff - CONFIG_ROM_SIZE) + 1)