From cadfb07dbecffb9b1808d313902d291f8326d9f8 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Tue, 18 Mar 2025 10:00:17 +0900 Subject: [PATCH] mb/nissa/var/meliks: Update GPP_E7 strap configuration Meliks uses GPP_E7 to determine the channel count of the RAM chip in romstage, move its configuration to early_gpio_table from override_gpio_table to be ready to use at that moment. And early stage meliks boards didn't implement the GPP_E7 strap but leaved it as NC. All of them used two channel ram chip, so add DN_20K for them not to disable any memory channel. Otherwise, they might not be able to boot since memory training will be failed due to the incorrect memory channel information. BUG=None BRANCH=nissa TEST=FW_NAME=meliks emerge-nissa coreboot Change-Id: Icf71c3a1f24d3dcbff6ba5e646e9f805144add71 Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/86908 Reviewed-by: Eric Lai Reviewed-by: Jayvik Desai Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Dinesh Gehlot Reviewed-by: Kapil Porwal --- src/mainboard/google/brya/variants/meliks/gpio.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/brya/variants/meliks/gpio.c b/src/mainboard/google/brya/variants/meliks/gpio.c index 6e11263075..d13ac2de9f 100644 --- a/src/mainboard/google/brya/variants/meliks/gpio.c +++ b/src/mainboard/google/brya/variants/meliks/gpio.c @@ -22,8 +22,6 @@ static const struct pad_config override_gpio_table[] = { /* D8 : SD_CLKREQ_ODL ==> NC */ PAD_NC(GPP_D8, NONE), - /* E7 : NC ==> GPP_E7_STRAP */ - PAD_CFG_GPI_LOCK(GPP_E7, NONE, LOCK_CONFIG), /* E14 : EDP_HPD ==> NC */ PAD_NC(GPP_E14, NONE), /* E20 : HDMI_DDC_SCL ==> NC */ @@ -82,6 +80,8 @@ static const struct pad_config override_gpio_table[] = { static const struct pad_config early_gpio_table[] = { /* A13 : GPP_A13 ==> GSC_SOC_INT_ODL */ PAD_CFG_GPI_APIC(GPP_A13, NONE, PLTRST, LEVEL, INVERT), + /* E7 : NC ==> GPP_E7_STRAP */ + PAD_CFG_GPI_LOCK(GPP_E7, DN_20K, LOCK_CONFIG), /* E12 : THC0_SPI1_IO1 ==> SOC_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E12, NONE, DEEP), /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */