From c8eb52c10c82893a928f1470ad7cb6ff37d89c30 Mon Sep 17 00:00:00 2001 From: Elmo Lan Date: Tue, 17 Jun 2025 17:15:42 +0800 Subject: [PATCH] ec/google/chromeec: Modify Realtek EC initialization timing The host must initialize necessary settings before accessing the Realtek EC via EMI. BUG=b:414474440 TEST=FW_NAME=brox_rtk_ec emerge-brox coreboot chromeos-bootimage flash to brox board with realtek rts5915 Boot normally and got those message from ap console: [DEBUG] Google Chrome EC uptime: 107.108 seconds [DEBUG] Google Chrome AP resets since EC boot: 2 [DEBUG] Google Chrome most recent AP reset causes: [DEBUG] 10.479: 32775 shutdown: entering G3 [DEBUG] 92.102: 8 reset: during EC initialization [DEBUG] Google Chrome EC reset flags at last EC boot: watchdog | sysjump [DEBUG] PNP: 0c09.0 init finished in 81 msecs Change-Id: I85ad210ccd40097dff552f7e72fe712e33cfd95f Signed-off-by: Elmo Lan Reviewed-on: https://review.coreboot.org/c/coreboot/+/88127 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Caveh Jalali Reviewed-by: Jayvik Desai --- src/ec/google/chromeec/ec.h | 5 -- src/ec/google/chromeec/ec_lpc.c | 3 -- src/ec/google/chromeec/rtk.c | 84 ++++++++++++++++++--------------- 3 files changed, 47 insertions(+), 45 deletions(-) diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 957adb4089..4b8d0958c3 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -486,11 +486,6 @@ const char *google_chromeec_acpi_name(const struct device *dev); #endif /* HAVE_ACPI_TABLES */ -/** - * Initialize the EC. - */ -void chipset_init(void); - /** * Read bytes from the EMI. * diff --git a/src/ec/google/chromeec/ec_lpc.c b/src/ec/google/chromeec/ec_lpc.c index 19139ccc07..f16d528833 100644 --- a/src/ec/google/chromeec/ec_lpc.c +++ b/src/ec/google/chromeec/ec_lpc.c @@ -446,14 +446,11 @@ int google_chromeec_command(struct chromeec_command *cec_command) return result; } -void __weak chipset_init(void) {} - static void lpc_ec_init(struct device *dev) { if (!dev->enabled) return; - chipset_init(); google_chromeec_init(); } diff --git a/src/ec/google/chromeec/rtk.c b/src/ec/google/chromeec/rtk.c index 6779d422f2..96ffbe5364 100644 --- a/src/ec/google/chromeec/rtk.c +++ b/src/ec/google/chromeec/rtk.c @@ -23,42 +23,7 @@ #define EMI_ADDR1 0xf2 /* The EMI base address 15-8*/ #define EMI_CTRL 0x30 -bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum) -{ - size_t i; - - printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %ld\n", port, length); - - if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) { - uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START)); - for (i = 0; i < length; ++i) { - dest[i] = p[i]; - if (csum) - *csum += dest[i]; - } - return true; - } - return false; -} - -bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum) -{ - size_t i; - - printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %ld\n", port, length); - - if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) { - uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START)); - for (i = 0; i < length; ++i) { - p[i] = msg[i]; - if (csum) - *csum += msg[i]; - } - return true; - } - - return false; -} +static bool is_emi_inited; static inline void sio_write_config(uint8_t reg, uint8_t value) { @@ -66,13 +31,15 @@ static inline void sio_write_config(uint8_t reg, uint8_t value) outb(value, SIO_DATA_PORT); } -void chipset_init(void) +static void host_emi_init(void) { /* * Due the hardware design, the RTS5915 EMI should be initiated by host sio command, * The EMI range is 256 bytes, chromeec needs two region for host command and ACPI * shared memory. */ + if (is_emi_inited) + return; printk(BIOS_INFO, "RTS5915 EMI: start init ...\n"); @@ -91,4 +58,47 @@ void chipset_init(void) sio_write_config(EMI_CTRL, 0x01); /* Enable EMI */ printk(BIOS_INFO, "RTS5915 EMI: done\n"); + + is_emi_inited = true; +} + +bool chipset_emi_read_bytes(u16 port, size_t length, u8 *dest, u8 *csum) +{ + size_t i; + + host_emi_init(); + + printk(BIOS_DEBUG, "RTS5915: read port 0x%x, size %zu\n", port, length); + + if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) { + uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START)); + for (i = 0; i < length; ++i) { + dest[i] = p[i]; + if (csum) + *csum += dest[i]; + } + return true; + } + return false; +} + +bool chipset_emi_write_bytes(u16 port, size_t length, u8 *msg, u8 *csum) +{ + size_t i; + + host_emi_init(); + + printk(BIOS_DEBUG, "RTS5915: write port 0x%x, size %zu\n", port, length); + + if (port >= EMI_RANGE_START && port <= EMI_RANGE_END) { + uint8_t *p = (uint8_t *)(HOSTCMD_PARAM_MEM_BASE + (port - EMI_RANGE_START)); + for (i = 0; i < length; ++i) { + p[i] = msg[i]; + if (csum) + *csum += msg[i]; + } + return true; + } + + return false; }