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src: Use of device_t is deprecated

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Change-Id: I9cebfc5c77187bd81094031c43ff6df094908417
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/27010
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2018-06-10 23:36:44 +02:00 • committed by Patrick Georgi
commit c8a649c08f
35 changed files with 109 additions and 104 deletions
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8
src/northbridge/amd/amdfam10/acpi.c
View file

@ -28,7 +28,7 @@
unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 lint)
{
device_t cpu;
struct device *cpu;
int cpu_index = 0;
for (cpu = all_devices; cpu; cpu = cpu->next) {
@ -47,7 +47,7 @@ unsigned long acpi_create_madt_lapic_nmis(unsigned long current, u16 flags, u8 l
unsigned long acpi_create_srat_lapics(unsigned long current)
{
device_t cpu;
struct device *cpu;
int cpu_index = 0;
for (cpu = all_devices; cpu; cpu = cpu->next) {
@ -193,7 +193,7 @@ void update_ssdtx(void *ssdtx, int i)
}
void northbridge_acpi_write_vars(device_t device)
void northbridge_acpi_write_vars(struct device *device)
{
/*
* If more than one physical CPU is installed, northbridge_acpi_write_vars()
@ -326,7 +326,7 @@ void northbridge_acpi_write_vars(device_t device)
acpigen_pop_len();
}
unsigned long northbridge_write_acpi_tables(device_t device,
unsigned long northbridge_write_acpi_tables(struct device *device,
unsigned long current,
struct acpi_rsdp *rsdp)
{

6
src/northbridge/amd/amdfam10/amdfam10.h
View file

@ -987,7 +987,7 @@ extern struct sys_info sysinfo_car;
#endif
*/
#ifndef __PRE_RAM__
device_t get_node_pci(u32 nodeid, u32 fn);
struct device *get_node_pci(u32 nodeid, u32 fn);
#endif
#ifdef __PRE_RAM__
@ -1021,10 +1021,10 @@ BOOL AMD_CB_ManualBUIDSwapList(u8 Node, u8 Link, const u8 **List);
struct acpi_rsdp;
#ifndef __SIMPLE_DEVICE__
unsigned long northbridge_write_acpi_tables(device_t device,
unsigned long northbridge_write_acpi_tables(struct device *device,
unsigned long start,
struct acpi_rsdp *rsdp);
void northbridge_acpi_write_vars(device_t device);
void northbridge_acpi_write_vars(struct device *device);
#endif
#endif /* AMDFAM10_H */

10
src/northbridge/amd/amdfam10/ht_config.c
View file

@ -26,7 +26,7 @@
struct dram_base_mask_t get_dram_base_mask(u32 nodeid)
{
struct dram_base_mask_t d;
device_t dev = __f1_dev[0];
struct device *dev = __f1_dev[0];
u32 temp;
temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16]
@ -57,7 +57,7 @@ void set_config_map_reg(struct bus *link)
tempreg |= (busn_max << 24)|(busn_min << 16)|(linkn << 8);
for (i = 0; i < sysconf.nodes; i++) {
device_t dev = __f1_dev[i];
struct device *dev = __f1_dev[i];
pci_write_config32(dev, 0xe0 + ht_c_index * 4, tempreg);
}
}
@ -68,7 +68,7 @@ void clear_config_map_reg(struct bus *link)
u32 ht_c_index = get_ht_c_index(link);
for (i = 0; i < sysconf.nodes; i++) {
device_t dev = __f1_dev[i];
struct device *dev = __f1_dev[i];
pci_write_config32(dev, 0xe0 + ht_c_index * 4, 0);
}
}
@ -190,8 +190,8 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
}
void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max)
{
u32 i;
u32 tempreg;

8
src/northbridge/amd/amdfam10/ht_config.h
View file

@ -19,8 +19,8 @@
typedef struct amdfam10_sysconf_t sys_info_conf_t;
/* FIXME */
u32 amdfam10_nodeid(device_t dev);
extern device_t __f1_dev[];
u32 amdfam10_nodeid(struct device *dev);
extern struct device *__f1_dev[];
struct dram_base_mask_t {
u32 base; //[47:27] at [28:8]
@ -46,8 +46,8 @@ void store_conf_mmio_addr(u32 nodeid, u32 linkn, u32 reg, u32 index,
u32 get_io_addr_index(u32 nodeid, u32 linkn);
u32 get_mmio_addr_index(u32 nodeid, u32 linkn);
void set_io_addr_reg(device_t dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max);
void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg,
u32 io_min, u32 io_max);
void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes);

12
src/northbridge/amd/amdfam10/misc_control.c
View file

@ -49,7 +49,7 @@
* implemented in a way to NOT DOING legacy VGA resource allocation on
* purpose :-(.
*/
static void mcf3_read_resources(device_t dev)
static void mcf3_read_resources(struct device *dev)
{
struct resource *resource;
unsigned char gart;
@ -75,14 +75,14 @@ static void mcf3_read_resources(device_t dev)
}
}
static void set_agp_aperture(device_t dev, uint32_t pci_id)
static void set_agp_aperture(struct device *dev, uint32_t pci_id)
{
uint32_t dword;
struct resource *resource;
resource = probe_resource(dev, 0x94);
if (resource) {
device_t pdev;
struct device *pdev;
u32 gart_base, gart_acr;
/* Remember this resource has been stored */
@ -117,7 +117,7 @@ static void set_agp_aperture(device_t dev, uint32_t pci_id)
}
}
static void mcf3_set_resources_fam10h(device_t dev)
static void mcf3_set_resources_fam10h(struct device *dev)
{
/* Set the gart aperture */
set_agp_aperture(dev, 0x1203);
@ -126,7 +126,7 @@ static void mcf3_set_resources_fam10h(device_t dev)
pci_dev_set_resources(dev);
}
static void mcf3_set_resources_fam15h_model10(device_t dev)
static void mcf3_set_resources_fam15h_model10(struct device *dev)
{
/* Set the gart aperture */
set_agp_aperture(dev, 0x1403);
@ -135,7 +135,7 @@ static void mcf3_set_resources_fam15h_model10(device_t dev)
pci_dev_set_resources(dev);
}
static void mcf3_set_resources_fam15h(device_t dev)
static void mcf3_set_resources_fam15h(struct device *dev)
{
/* Set the gart aperture */
set_agp_aperture(dev, 0x1603);

2
src/northbridge/amd/amdfam10/northbridge.h
View file

@ -16,7 +16,7 @@
#ifndef NORTHBRIDGE_AMD_AMDFAM10_H
#define NORTHBRIDGE_AMD_AMDFAM10_H
u32 amdfam10_scan_root_bus(device_t root, u32 max);
u32 amdfam10_scan_root_bus(struct device *root, u32 max);
void get_pci1234(void);
#endif /* NORTHBRIDGE_AMD_AMDFAM10_H */

10
src/northbridge/amd/amdfam10/util.c
View file

@ -189,7 +189,7 @@ static void showmmio(int level, u8 which, u32 base, u32 lim)
* @param dev A 32-bit number in the standard bus/dev/fn format which is used
* raw config space.
*/
static void showalldram(int level, device_t dev)
static void showalldram(int level, struct device *dev)
{
u8 reg;
for (reg = DRAM_ROUTE_START; reg <= DRAM_ROUTE_END; reg += 8) {
@ -207,7 +207,7 @@ static void showalldram(int level, device_t dev)
* @param dev A 32-bit number in the standard bus/dev/fn format which is used
* raw config space.
*/
static void showallmmio(int level, device_t dev)
static void showallmmio(int level, struct device *dev)
{
u8 reg;
for (reg = MMIO_ROUTE_START; reg <= MMIO_ROUTE_END; reg += 8) {
@ -225,7 +225,7 @@ static void showallmmio(int level, device_t dev)
* @param dev A 32-bit number in the standard bus/dev/fn format which is used
* raw config space.
*/
static void showallpciio(int level, device_t dev)
static void showallpciio(int level, struct device *dev)
{
u8 reg;
for (reg = PCIIO_ROUTE_START; reg <= PCIIO_ROUTE_END; reg += 8) {
@ -243,7 +243,7 @@ static void showallpciio(int level, device_t dev)
* @param dev A 32-bit number in the standard bus/dev/fn format which is used
* raw config space.
*/
static void showallconfig(int level, device_t dev)
static void showallconfig(int level, struct device *dev)
{
u8 reg;
for (reg = CONFIG_ROUTE_START; reg <= CONFIG_ROUTE_END; reg += 4) {
@ -260,7 +260,7 @@ static void showallconfig(int level, device_t dev)
* @param dev A 32-bit number in the standard bus/dev/fn format which is used
* raw config space.
*/
void showallroutes(int level, device_t dev)
void showallroutes(int level, struct device *dev)
{
showalldram(level, dev);
showallmmio(level, dev);

12
src/northbridge/amd/lx/northbridge.c
View file

@ -287,11 +287,11 @@ int sizeram(void)
return sizem;
}
static void enable_shadow(device_t dev)
static void enable_shadow(struct device *dev)
{
}
static void northbridge_init(device_t dev)
static void northbridge_init(struct device *dev)
{
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@ -348,11 +348,11 @@ static const struct pci_driver northbridge_driver __pci_driver = {
#include <cbmem.h>
static void pci_domain_set_resources(device_t dev)
static void pci_domain_set_resources(struct device *dev)
{
int idx;
u32 tomk;
device_t mc_dev;
struct device *mc_dev;
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@ -371,7 +371,7 @@ static void pci_domain_set_resources(device_t dev)
assign_resources(dev->link_list);
}
static void pci_domain_enable(device_t dev)
static void pci_domain_enable(struct device *dev)
{
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
@ -393,7 +393,7 @@ static struct device_operations pci_domain_ops = {
.enable = pci_domain_enable,
};
static void cpu_bus_init(device_t dev)
static void cpu_bus_init(struct device *dev)
{
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);

4
src/northbridge/amd/pi/00630F01/iommu.c
View file

@ -19,7 +19,7 @@
#include <device/pci_ops.h>
#include <lib.h>
static void iommu_read_resources(device_t dev)
static void iommu_read_resources(struct device *dev)
{
struct resource *res;
@ -35,7 +35,7 @@ static void iommu_read_resources(device_t dev)
res->flags = IORESOURCE_MEM;
}
static void iommu_set_resources(device_t dev)
static void iommu_set_resources(struct device *dev)
{
struct resource *res;