From c852840f11871a5bf8e42be6df79db9fa02a376b Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Fri, 9 Jan 2026 08:07:27 -0800 Subject: [PATCH] soc/intel/pantherlake: Disable TCC MSR lock in FSP Since Panther Lake, the FSP locks the TCC (Thermal Control Circuit) MSR by default. However, Linux-based thermal management systems typically configure this register from the operating system rather than the firmware. Locking the TCC MSR in firmware prevents the OS from adjusting thermal parameters as needed, potentially impacting system thermal management and flexibility. This commit explicitly sets the TccOffsetLock field to 0 in the FSP-M configuration, ensuring that the TCC MSR remains unlocked after firmware initialization. BUG=b:474002582 TEST=MSR 0x1A2 is writable from the OS, as indicated by the successful operation of /sys/bus/pci/devices/0000:00:04/tcc_offset_degree_celsius on a Fatcat device. Change-Id: I445bc1408018d3de82919e46c8a368d93bbb1a77 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/90718 Reviewed-by: Alicja Michalska Reviewed-by: Guvendik, Bora Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- src/soc/intel/pantherlake/romstage/fsp_params.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c index 5ec92bb80f..d6f628b36a 100644 --- a/src/soc/intel/pantherlake/romstage/fsp_params.c +++ b/src/soc/intel/pantherlake/romstage/fsp_params.c @@ -313,6 +313,7 @@ static void fill_fspm_thermal_params(FSP_M_CONFIG *m_cfg, const struct soc_intel_pantherlake_config *config) { m_cfg->TccActivationOffset = config->tcc_offset; + m_cfg->TccOffsetLock = 0; } static const struct soc_intel_pantherlake_power_map *get_map(const struct soc_intel_pantherlake_config *config)