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lib/spd_bin: Add support for DDR5 SPD parsing

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Without explicit DDR5 support, print_spd_info() was decoding DDR5 DIMMs
with the DDR4 SPD layout, so banks, ranks, rows, columns, and module
size were all displaying incorrect values.

Add DDR5-specific decoding in spd_bin.c using JESD400-5 byte positions.
Define these offsets in ddr5.h and branch in each getter when
dram_type is DDR5 so printed SPD info matches the actual module.

Fix printk reporting DIMM module size to only report "per channel" when
the DIMM actually contains multiple channels.

TEST=build/boot on out-of-tree board Erying SRMJ4 and Starlabs Starbook
MTL. Verify DIMM info printed in cbmem console is correct.

Change-Id: I7f418db3f89c67c2a71b2c327bb511a78faf7300
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/91145
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Matt DeVillier 2026-02-09 09:00:39 -06:00
commit c731fd720c
2 changed files with 77 additions and 9 deletions
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9
src/include/device/dram/ddr5.h
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@ -15,6 +15,15 @@
/** Maximum SPD size supported */
#define SPD_SIZE_MAX_DDR5 1024
/* DDR5 SPD byte offsets */
#define DDR5_SPD_DENSITY_PACKAGE 4
#define DDR5_SPD_ADDRESSING 5
#define DDR5_SPD_IO_WIDTH 6
#define DDR5_SPD_BANKS 7
#define DDR5_SPD_MODULE_ORG 234
#define DDR5_SPD_CHANNEL_BUS_WIDTH 235
#define DDR5_SPD_MIN_LEN 236
enum spd_dimm_type_ddr5 {
SPD_DDR5_DIMM_TYPE_RDIMM = 0x01,
SPD_DDR5_DIMM_TYPE_UDIMM = 0x02,