From c6f82a843223786f91afeabf8f70eee5de803ffa Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 28 Jan 2025 22:40:07 +0530 Subject: [PATCH] mainboard/google/fatcat: Increase RW_SECTION_A/B size by 1MB The google/fatcat board's flash layout was modified to increase the size of RW_SECTION_A and RW_SECTION_B by 1MB each (from 7MB to 8MB). The RW_UNUSED region size was reduced to accommodate the increased RW_SECTION sizes. This change provides additional space in the RW slots to accommodate growth in the payload (depthcharge). TEST=Built and flashed the image. Verified that both RW_SECTION_A and RW_SECTION_B are populated with the correct firmware components and that the system boots successfully. Change-Id: Ie489d53cef00ddc2dc6beef891f870c6bc0562a8 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/86202 Tested-by: build bot (Jenkins) Reviewed-by: Jon Murphy Reviewed-by: Jayvik Desai Reviewed-by: Karthik Ramasubramanian --- src/mainboard/google/fatcat/chromeos.fmd | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd index ca29bbce57..0ff14e3691 100644 --- a/src/mainboard/google/fatcat/chromeos.fmd +++ b/src/mainboard/google/fatcat/chromeos.fmd @@ -4,11 +4,20 @@ FLASH 32M { SI_ME } SI_BIOS 24M { - RW_SECTION_A 7M { + RW_SECTION_A 8M { VBLOCK_A 8K FW_MAIN_A(CBFS) RW_FWID_A 64 } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 8M { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -22,17 +31,8 @@ FLASH 32M { RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } - # This section starts at the 16M boundary in SPI flash. - # PTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7M { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_LEGACY(CBFS) 1M - RW_UNUSED 4M + RW_UNUSED 2M # Make WP_RO region align with SPI vendor # memory protected range specification. WP_RO 4M {