diff --git a/src/mainboard/google/fatcat/chromeos.fmd b/src/mainboard/google/fatcat/chromeos.fmd
index ca29bbce57..0ff14e3691 100644
--- a/src/mainboard/google/fatcat/chromeos.fmd
+++ b/src/mainboard/google/fatcat/chromeos.fmd
@@ -4,11 +4,20 @@ FLASH 32M {
 		SI_ME
 	}
 	SI_BIOS 24M {
-		RW_SECTION_A 7M {
+		RW_SECTION_A 8M {
 			VBLOCK_A 8K
 			FW_MAIN_A(CBFS)
 			RW_FWID_A 64
 		}
+		# This section starts at the 16M boundary in SPI flash.
+		# PTL does not support a region crossing this boundary,
+		# because the SPI flash is memory-mapped into two non-
+		# contiguous windows.
+		RW_SECTION_B 8M {
+			VBLOCK_B 8K
+			FW_MAIN_B(CBFS)
+			RW_FWID_B 64
+		}
 		RW_MISC 1M {
 			UNIFIED_MRC_CACHE(PRESERVE) 128K {
 				RECOVERY_MRC_CACHE 64K
@@ -22,17 +31,8 @@ FLASH 32M {
 			RW_VPD(PRESERVE) 8K
 			RW_NVRAM(PRESERVE) 24K
 		}
-		# This section starts at the 16M boundary in SPI flash.
-		# PTL does not support a region crossing this boundary,
-		# because the SPI flash is memory-mapped into two non-
-		# contiguous windows.
-		RW_SECTION_B 7M {
-			VBLOCK_B 8K
-			FW_MAIN_B(CBFS)
-			RW_FWID_B 64
-		}
 		RW_LEGACY(CBFS) 1M
-		RW_UNUSED 4M
+		RW_UNUSED 2M
 		# Make WP_RO region align with SPI vendor
 		# memory protected range specification.
 		WP_RO 4M {