Mods for the new via mainboard.
This commit is contained in:
Ronald G. Minnich
parent
6bc6af0c08
commit
c5a3540037
8 changed files with 521 additions and 0 deletions
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@ -6,6 +6,8 @@ CPUFLAGS += -DINTEL_PPRO_MTRR
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CPUFLAGS += -DPM133_NVRAM -DPM133_KEYBOARD
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DSERIAL_CONSOLE
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# mainboard-dependent.
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CPUFLAGS += -DPM_DEVFN=0x3c
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# If you enable FIXED_AND_VARIABLE it never makes it to the kernel!
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# you have to only enable variable.
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# 1/25/01. Things just stopped working for no reason I can see (RGM).
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@ -9,6 +9,8 @@ CPUFLAGS += -DSERIAL_CONSOLE
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# If you enable FIXED_AND_VARIABLE it never makes it to the kernel!
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# you have to only enable variable.
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#CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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# mainboard-dependent.
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CPUFLAGS += -DPM_DEVFN=0x3c
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CPUFLAGS += -DRAMTEST
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# This makes it fail sooner ...
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#CPUFLAGS += -DINBUF_COPY
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165
romimages/RON_VT5426/Makefile
Normal file
165
romimages/RON_VT5426/Makefile
Normal file
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@ -0,0 +1,165 @@
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CPUFLAGS=-DPM133 -Di386 -Di486 -Di686 -Di586 -D__KERNEL__
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# Well, we have old silicon
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CPUFLAGS += -DPM133_REV_CD_CE
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CPUFLAGS += -DINTEL_BRIDGE_CONFIG
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CPUFLAGS += -DINTEL_PPRO_MTRR
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CPUFLAGS += -DPM133_NVRAM -DPM133_KEYBOARD
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CPUFLAGS += -DNEWPCI
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CPUFLAGS += -DSERIAL_CONSOLE
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# If you enable FIXED_AND_VARIABLE it never makes it to the kernel!
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# you have to only enable variable.
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# 1/25/01. Things just stopped working for no reason I can see (RGM).
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# First test: enable fixed and variable MTRRs.
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# This wasn't the problem (My stupidity was) but it works ok, so leave
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# it in.
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CPUFLAGS += -DENABLE_FIXED_AND_VARIABLE_MTRRS
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# mainboard-dependent.
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CPUFLAGS += -DPM_DEVFN=0x8c
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CPUFLAGS += -DRAMTEST
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# This makes it fail sooner ...
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#CPUFLAGS += -DINBUF_COPY
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CPUFLAGS += -DCMD_LINE='"ro root=/dev/hda1 console=ttyS0,115200 single "'
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TOP=../..
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INCLUDES=-nostdinc -I $(TOP)/src/include
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NOOPT_CFLAGS=$(INCLUDES) $(CPUFLAGS) -Wall
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CFLAGS=$(NOOPT_CFLAGS) -O2
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OBJECTS=crt0.o hardwaremain.o linuxbiosmain.o
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OBJECTS += mainboard.o mtrr.o subr.o fill_inbuf.o params.o
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OBJECTS += southbridge.o northbridge.o
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OBJECTS += printk.o vsprintf.o
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OBJECTS += newpci.o linuxpci.o
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OBJECTS += cpuid.o
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#OBJECTS += intel_irq_tables.o
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OBJECTS += serial_subr.o
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OBJECTS += mpspec.o
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OBJECTS += microcode.o
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OBJECTS += keyboard.o
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#LINUX=$(TOP)/../linux-2.4.0-test6.via/
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LINUX=$(TOP)/../linux-2.4.0-via/
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LINK = ld -T ldscript.ld -o $@ $(OBJECTS)
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CC=cc $(CFLAGS)
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CCASM=cc -I$(TOP)/chip/intel $(CFLAGS)
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all: romimage
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floppy: all
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mcopy -o romimage a:
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# here's the problem: we shouldn't assume we come up with more than
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# 64K of FLASH up. SO we need a working linuxbios at the tail, and it will
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# enable all flash and then gunzip the linuxbios. As a result,
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# we need the vmlinux.bin.gz padded out and then cat the linuxbios.rom
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# at then end. We always copy it to /tmp so that a waiting root shell
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# can put it on the floppy (see ROOTDOIT)
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romimage: linuxbios.rom vmlinux.bin.gz.block
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cat vmlinux.bin.gz.block linuxbios.rom > romimage
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linuxbios.rom: linuxbios.strip mkrom
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./mkrom -s 64 -f -o linuxbios.rom linuxbios.strip
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linuxbios.strip: linuxbios
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objcopy -O binary -R .note -R .comment -S linuxbios linuxbios.strip
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linuxbios: $(OBJECTS) vmlinux.bin.gz
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@rm -f biosobject
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$(LINK)
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nm -n linuxbios > linuxbios.map
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# crt0 actually includes .inc files.
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# For self-documenting purposes, we put the FULL PATH of the
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# .inc files (relative to $TOP/src) in crt0.S.
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# So, for example, earlymtrr.inc is included as cpu/p6/earlymtrr.inc
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# To make this work, add the extra -I $(TOP)/src here.
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crt0.s: crt0.S
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$(CCASM) -I $(TOP)/src -E crt0.S > crt0.s
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crt0.o : crt0.s
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$(CCASM) -c crt0.s
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mkrom: $(TOP)/mkrom/mkrom.c
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cc -o mkrom $<
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linuxbiosmain.o: $(TOP)/src/lib/linuxbiosmain.c
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cc $(CFLAGS) -c $<
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mainboard.o: $(TOP)/src/mainboard/via/vt5426/mainboard.c
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cc $(CFLAGS) -c $<
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fill_inbuf.o: $(TOP)/src/lib/fill_inbuf.c
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cc $(CFLAGS) -c $<
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params.o: $(TOP)/src/lib/params.c
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cc $(CFLAGS) $(LINUXINCLUDE) -c $<
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hardwaremain.o: $(TOP)/src/lib/hardwaremain.c
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cc $(CFLAGS) -c $<
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southbridge.o: $(TOP)/src/southbridge/via/vt82c686/southbridge.c
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cc $(CFLAGS) -c $<
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northbridge.o: $(TOP)/src/northbridge/via/vt8601/northbridge.c
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cc $(CFLAGS) -c $<
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pci.o: $(TOP)/src/lib/pci.c
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cc $(CFLAGS) -c $<
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# not on this machine, not yet.
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#intel_irq_tables.o: ../../chip/intel/intel_irq_tables.c
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# cc $(CFLAGS) -o $@ -c $<
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mtrr.o: $(TOP)/src/cpu/p6/mtrr.c
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cc $(CFLAGS) -c $<
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subr.o: $(TOP)/src/lib/subr.c
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cc $(CFLAGS) -c $<
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keyboard.o: $(TOP)/src/pc80/keyboard.c
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cc $(CFLAGS) -c $<
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cpuid.o: $(TOP)/src/cpu/p5/cpuid.c
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cc $(CFLAGS) -c $<
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mpspec.o: $(TOP)/src/cpu/p6/mpspec.c
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$(CC) $(CFLAGS) -c $<
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microcode.o: $(TOP)/src/cpu/p6/microcode.c
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$(CC) $(CFLAGS) -c $<
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serial_subr.o: $(TOP)/src/lib/serial_subr.c
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cc $(CFLAGS) -c $<
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printk.o: $(TOP)/src/lib/printk.c
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cc $(CFLAGS) -c $<
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vsprintf.o: $(TOP)/src/lib/vsprintf.c
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cc $(CFLAGS) -c $<
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newpci.o: $(TOP)/src/lib/newpci.c
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cc $(CFLAGS) -c $<
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linuxpci.o: $(TOP)/src/lib/linuxpci.c
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cc $(CFLAGS) -c $<
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vmlinux.bin.gz.block: vmlinux.bin.gz
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dd conv=sync bs=448k if=vmlinux.bin.gz of=vmlinux.bin.gz.block
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vmlinux.bin.gz: vmlinux.bin
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gzip -f -3 vmlinux.bin
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vmlinux.bin: $(LINUX)/vmlinux
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objcopy -O binary -R .note -R .comment -S $< vmlinux.bin
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alltags:
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gctags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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etags ../inflate/*.c ../../lib/*.c ../../chip/intel/*.c
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clean::
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rm -f linuxbios.* vmlinux.* *.o mkrom xa? *~ linuxbios romimage crt0.s
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rm -f a.out *.s *.l
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rm -f TAGS tags
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113
romimages/RON_VT5426/crt0.S
Normal file
113
romimages/RON_VT5426/crt0.S
Normal file
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@ -0,0 +1,113 @@
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/*
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* $ $
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*
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*/
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#include <asm.h>
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#include <intel.h>
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#include <pciconf.h>
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/*
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* This is the entry code (the mkrom(8) utility makes a jumpvector
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* to this adddess.
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*
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* When we get here we are in x86 real mode.
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*
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* %cs = 0xf000 %ip = 0x0000
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* %ds = 0x0000 %es = 0x0000
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* %dx = 0x0yxx (y = 3 for i386, 5 for pentium, 6 for P6,
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* where x is undefined)
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* %fl = 0x0002
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*/
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.text
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.code16
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#include <cpu/p5/start32.inc>
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/* turn on serial */
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#include <southbridge/via/vt82c686/setup_serial.inc>
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#include <pc80/serial.inc>
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#include <pc80/i8259.inc>
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/*
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*/
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TTYS0_TX_STRING($ttyS0_test)
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/* initialize the RAM */
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/* different for each motherboard */
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#include <northbridge/via/vt8601/raminitspd.inc>
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#include <sdram/smbus_pcibus.inc>
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#include <sdram/generic_sdram.inc>
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#ifdef RAMTEST
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#include <ram/ramtest.inc>
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#include <cpu/p6/earlymtrr.inc>
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mov $0x00000000, %eax
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mov $0x0009ffff, %ebx
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mov $16, %ecx
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CALLSP(ramtest)
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#endif
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/*
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* Copy data into RAM and clear the BSS. Since these segments
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* isn't really that big we just copy/clear using bytes, not
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* double words.
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*/
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intel_chip_post_macro(0x11) /* post 11 */
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TTYS0_TX_STRING($str_after_ram)
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cld /* clear direction flag */
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leal EXT(_ldata), %esi
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leal EXT(_data), %edi
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movl $EXT(_eldata), %ecx
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subl %esi, %ecx
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jz .Lnodata /* should not happen */
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rep
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movsb
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.Lnodata:
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intel_chip_post_macro(0x12) /* post 12 */
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TTYS0_TX_STRING($str_after_copy)
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/** clear stack */
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xorl %edi, %edi
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movl $_PDATABASE, %ecx
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xorl %eax, %eax
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rep
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stosb
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/** clear bss */
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leal EXT(_bss), %edi
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movl $EXT(_ebss), %ecx
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subl %edi, %ecx
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jz .Lnobss
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xorl %eax, %eax
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rep
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stosb
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.Lnobss:
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/*
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* Now we are finished. Memory is up, data is copied and
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* bss is cleared. Now we call the ``main´´ routine and
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* let it do the rest.
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*/
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intel_chip_post_macro(0xfe) /* post fe */
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TTYS0_TX_STRING($str_pre_main)
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/* set new stack */
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movl $_PDATABASE, %esp
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/* memory is up. Let's do the rest in C -- much easier. */
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call EXT(intel_main)
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/*NOTREACHED*/
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.Lhlt: hlt
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jmp .Lhlt
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ttyS0_test: .string "\r\n\r\nHello world!!\r\n"
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str_after_ram: .string "Ram Initialize?\r\n"
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str_after_copy: .string "after copy?\r\n"
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str_pre_main: .string "before main\r\n"
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newline: .string "\r\n"
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116
romimages/RON_VT5426/ldscript.ld
Normal file
116
romimages/RON_VT5426/ldscript.ld
Normal file
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@ -0,0 +1,116 @@
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/*
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* Bootstrap code for the STPC Consumer
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* Copyright (c) 1999 by Net Insight AB. All Rights Reserved.
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*
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* $Id$
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*
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*/
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/* oh, barf. This won't work if all you use is .o's. -- RGM */
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/*
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* Written by Johan Rydberg, based on work by Daniel Kahlin.
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*/
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/*
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* We use ELF as output format. So that we can
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* debug the code in some form.
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*/
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OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386")
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OUTPUT_ARCH(i386)
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/*
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* Memory map:
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*
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* 0x00000 (4*4096 bytes) : stack
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* 0x04000 (4096 bytes) : private data
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* 0x05000 : data space
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* 0x90000 : kernel stack
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* 0xf0000 (64 Kbyte) : EPROM
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*/
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MEMORY
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{
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ram (rwx) : ORIGIN = 0x00000000, LENGTH = 128M /* 128 MB memory is
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* max for STPC */
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rom (rx) : ORIGIN = 0x000f0000, LENGTH = 128K /* 128 K EPROM */
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}
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_PDATABASE = 0x04000;
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_RAMBASE = 0x05000;
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_KERNSTK = 0x90000;
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/* should be parameterized but is not, yuck! */
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/*
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_ROMBASE = 0xe0000;
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*/
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_ROMBASE = 0xf0000;
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/*
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* Entry point is not really nececary, since the mkrom(8)
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* tool creates a entry point that jumps to $0xc000:0x0000.
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*/
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/* baloney, but ... RGM*/
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ENTRY(_start)
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SECTIONS {
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/*
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* First we place the code and read only data (typically const declared).
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* This get placed in rom.
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*/
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.text _ROMBASE : {
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_text = .;
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*(.text);
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*(.rodata);
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_etext = .;
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}
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_pdata = .;
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/*
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.pdata _PDATABASE : AT ( LOADADDR(.text) + SIZEOF(.text) +
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SIZEOF(.rodata)) {
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*/
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.pdata _PDATABASE : AT ( _etext ) {
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*(.pdata);
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}
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_epdata = LOADADDR(.pdata) + SIZEOF(.pdata);
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/*
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* After the code we place initialized data (typically initialized
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* global variables). This gets copied into ram by startup code.
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* __data_start and __data_end shows where in ram this should be placed,
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* whereas __data_loadstart and __data_loadend shows where in rom to
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* copy from.
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*/
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.data _RAMBASE : AT ( LOADADDR(.pdata) + SIZEOF(.pdata) ) {
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_data = .;
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*(.data)
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*(.sdata)
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*(.sdata2)
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*(.got)
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_edata = .;
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}
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_ldata = LOADADDR(.data);
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_eldata = LOADADDR(.data) + SIZEOF(.data);
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/*
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* bss does not contain data, it is just a space that should be zero
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* initialized on startup. (typically uninitialized global variables)
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* crt0.S fills between __bss_start and __bss_end with zeroes.
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*/
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.bss ( ADDR(.data) + SIZEOF(.data) ) : {
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_bss = .;
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*(.bss)
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*(.sbss)
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*(COMMON)
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_ebss = .;
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_heap = .;
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}
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}
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/*
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* This provides the start and end address for the whole image
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*/
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_image = LOADADDR(.text);
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_eimage = LOADADDR(.data) + SIZEOF(.data);
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/* EOF */
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9
src/mainboard/via/vt5426/Config
Normal file
9
src/mainboard/via/vt5426/Config
Normal file
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@ -0,0 +1,9 @@
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northbridge via/vt8601
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southbridge via/vt82c686
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superio via/vt82c686
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option ENABLE_FIXED_AND_VARIABLE_MTRRS
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object mainboard.o
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keyboard pc80
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cpu p5
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cpu p6
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6
src/mainboard/via/vt5426/mainboard.c
Normal file
6
src/mainboard/via/vt5426/mainboard.c
Normal file
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@ -0,0 +1,6 @@
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void
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mainboard_fixup()
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{
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void southbridge_fixup(void);
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southbridge_fixup();
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}
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@ -0,0 +1,108 @@
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/*
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* setup_serial.inc: setup serial port for m1535
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*
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*
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* Copyright 2001 Acer Labs Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
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||||
* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
|
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*
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*
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* Reference:
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* 1. M1535D document
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* $Id$
|
||||
*/
|
||||
/*
|
||||
* Super I/O Logical Device 4 (UART1)
|
||||
Reg 0x30 [0] = 1 -- UART1 Enable
|
||||
Reg 0x60 [7:0] = 0x03 -- The high address UART1's I/O base address
|
||||
Reg 0x61 [7:0] = 0xF8 -- The low address UART1's I/O base address
|
||||
Reg 0x70 [7:0] = 0x04 -- IRQ[4]
|
||||
Reg 0xF0 [7:0] = 0x00
|
||||
Reg 0xf1 [7:0] = 0x00
|
||||
Reg 0xf2 [7:0] = 0x00
|
||||
|
||||
assume I/O port address is 0x3F0
|
||||
*/
|
||||
|
||||
// 1 ;enter configuration mode
|
||||
movw $0x3f0,%dx
|
||||
movb $0x51,%al
|
||||
outb %al,%dx
|
||||
movw $0x23,%ax
|
||||
outb %al,%dx
|
||||
|
||||
// 2 ;program logical device 4
|
||||
movw $0x3f0,%dx
|
||||
movb $0x07,%al
|
||||
outb %al,%dx //point to device select register
|
||||
movw $0x3f1,%dx
|
||||
movb $0x04,%al
|
||||
outb %al,%dx //point to device 4
|
||||
|
||||
movw $0x3f0,%dx
|
||||
movb $0x30,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0x01,%al
|
||||
outb %al,%dx //enable UART1 controller
|
||||
|
||||
movw $0x3f0,%dx
|
||||
movb $0x60,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0x03,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f0,%dx
|
||||
movb $0x61,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0xf8,%al
|
||||
outb %al,%dx //select UART1's I/O base address to $0x3F$0x8
|
||||
|
||||
movw $0x3f0,%dx
|
||||
movb $0x70,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0x04,%al
|
||||
outb %al,%dx //select IRQ 4 used by UART1
|
||||
|
||||
movw $0x3f0,%dx
|
||||
movb $0xf0,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0x00,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f0,%dx
|
||||
movb $0xf1,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0x00,%al
|
||||
outb %al,%dx
|
||||
|
||||
movw $0x3f0,%dx
|
||||
movb $0xf2,%al
|
||||
outb %al,%dx
|
||||
movw $0x3f1,%dx
|
||||
movb $0x00,%al
|
||||
outb %al,%dx
|
||||
|
||||
// 3. exit configuration mode
|
||||
movw $0x3f0,%dx
|
||||
movb $0xbb,%al
|
||||
outb %al,%dx
|
||||
|
||||
|
||||
|
||||
|
||||
Loading…
Add table
Add a link
Reference in a new issue