diff --git a/src/mainboard/siemens/mc_rpl/Makefile.mk b/src/mainboard/siemens/mc_rpl/Makefile.mk
index b52fe96f2e..75988f66ca 100644
--- a/src/mainboard/siemens/mc_rpl/Makefile.mk
+++ b/src/mainboard/siemens/mc_rpl/Makefile.mk
@@ -6,7 +6,6 @@ romstage-y += romstage_fsp_params.c
 romstage-y += memory.c
 
 ramstage-y += mainboard.c
-ramstage-y += ramstage.c
 
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
 
diff --git a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
index e27b1773ba..55c68e5e25 100644
--- a/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
+++ b/src/mainboard/siemens/mc_rpl/include/baseboard/variants.h
@@ -7,26 +7,6 @@
 #include <soc/meminit.h>
 #include <stdint.h>
 
-enum adl_boardid {
-	/* ADL-P LPDDR4 RVPs */
-	ADL_P_LP4_1 = 0x10,
-	ADL_P_LP4_2 = 0x11,
-	/* ADL-P DDR5 RVPs */
-	ADL_P_DDR5_1 = 0x12,
-	ADL_P_DDR5_2 = 0x16,
-	/* ADL-P LPDDR5 RVP */
-	ADL_P_LP5_1 = 0x13,
-	ADL_P_LP5_2 = 0x17,
-	/* ADL-P DDR4 RVPs */
-	ADL_P_DDR4_1 = 0x14,
-	ADL_P_DDR4_2 = 0x3F,
-	/* ADL-M LP4 and LP5 RVPs */
-	ADL_M_LP4 = 0x1,
-	ADL_M_LP5 = 0x2,
-	/* ADL-N LP5 RVP */
-	ADL_N_LP5 = 0x7,
-};
-
 /* Functions to configure GPIO as per variant schematics */
 void variant_configure_gpio_pads(void);
 void variant_configure_early_gpio_pads(void);
@@ -36,18 +16,4 @@ const struct mb_cfg *variant_memory_params(void);
 void rpl_memory_params(FSPM_UPD *memupd);
 void variant_configure_fspm(FSPM_UPD *memupd);
 
-/* Modify devictree settings during ramstage */
-void variant_devtree_update(void);
-struct cpu_power_limits {
-	uint16_t mchid;
-	u8 cpu_tdp;
-	unsigned int pl1_min_power;
-	unsigned int pl1_max_power;
-	unsigned int pl2_min_power;
-	unsigned int pl2_max_power;
-	unsigned int pl4_power;
-};
-/* Modify Power Limit devictree settings during ramstage */
-void variant_update_power_limits(void);
-
 #endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/siemens/mc_rpl/mainboard.c b/src/mainboard/siemens/mc_rpl/mainboard.c
index 26d1947e73..0e14064684 100644
--- a/src/mainboard/siemens/mc_rpl/mainboard.c
+++ b/src/mainboard/siemens/mc_rpl/mainboard.c
@@ -111,12 +111,6 @@ static void mainboard_init(void *chip_info)
 {
 	variant_configure_gpio_pads();
 
-	variant_devtree_update();
-}
-
-void __weak variant_devtree_update(void)
-{
-	/* Override dev tree settings per board */
 }
 
 struct chip_operations mainboard_ops = {
diff --git a/src/mainboard/siemens/mc_rpl/ramstage.c b/src/mainboard/siemens/mc_rpl/ramstage.c
deleted file mode 100644
index c1d50f0a00..0000000000
--- a/src/mainboard/siemens/mc_rpl/ramstage.c
+++ /dev/null
@@ -1,68 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-#include <acpi/acpi_device.h>
-#include <baseboard/variants.h>
-#include <console/console.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include <soc/gpio_soc_defs.h>
-#include <soc/pci_devs.h>
-#include <soc/soc_chip.h>
-#include <static.h>
-#include <string.h>
-#include <drivers/intel/dptf/chip.h>
-#include <intelblocks/power_limit.h>
-
-const struct cpu_power_limits limits[] = {
-	/* SKU_ID, TDP (Watts), pl1_min, pl1_max, pl2_min, pl2_max, PL4 */
-	/* PL2 values are for performance configuration */
-	{ PCI_DID_INTEL_ADL_P_ID_7, 15, 3000, 15000,  55000,  55000, 123000 },
-	{ PCI_DID_INTEL_ADL_P_ID_6, 15, 3000, 15000,  55000,  55000, 123000 },
-	{ PCI_DID_INTEL_ADL_P_ID_5, 28, 4000, 28000,  64000,  64000, 140000 },
-	{ PCI_DID_INTEL_ADL_P_ID_3, 28, 4000, 28000,  64000,  64000, 140000 },
-	{ PCI_DID_INTEL_ADL_P_ID_3, 45, 5000, 45000, 115000, 115000, 215000 },
-	{ PCI_DID_INTEL_ADL_N_ID_1, 15, 3000, 15000,  35000,  35000,  83000 },
-	{ PCI_DID_INTEL_ADL_N_ID_2,  6, 3000,  6000,  25000,  25000,  78000 },
-	{ PCI_DID_INTEL_ADL_N_ID_3,  6, 3000,  6000,  25000,  25000,  78000 },
-	{ PCI_DID_INTEL_ADL_N_ID_4,  6, 3000,  6000,  25000,  25000,  78000 },
-	{ PCI_DID_INTEL_ADL_N_ID_5,  6, 3000,  6000,  25000,  25000,  78000 },
-};
-
-WEAK_DEV_PTR(dptf_policy);
-void variant_update_power_limits(void)
-{
-	const struct device *policy_dev = DEV_PTR(dptf_policy);
-	if (!policy_dev)
-		return;
-
-	struct drivers_intel_dptf_config *config = config_of(policy_dev);
-
-	uint16_t mchid = pci_s_read_config16(PCI_DEV(0, 0, 0), PCI_DEVICE_ID);
-
-	u8 tdp = get_cpu_tdp();
-
-	for (size_t i = 0; i < ARRAY_SIZE(limits); i++) {
-		if (mchid == limits[i].mchid && tdp == limits[i].cpu_tdp) {
-			struct dptf_power_limits *settings = &config->controls.power_limits;
-			config_t *conf = config_of_soc();
-			struct soc_power_limits_config *soc_config = conf->power_limits_config;
-			settings->pl1.min_power = limits[i].pl1_min_power;
-			settings->pl1.max_power = limits[i].pl1_max_power;
-			settings->pl2.min_power = limits[i].pl2_min_power;
-			settings->pl2.max_power = limits[i].pl2_max_power;
-			soc_config->tdp_pl4 = DIV_ROUND_UP(limits[i].pl4_power,
-									MILLIWATTS_TO_WATTS);
-			printk(BIOS_INFO, "Overriding power limits PL1 (%u, %u) PL2 (%u, %u) PL4 (%u)\n",
-					limits[i].pl1_min_power,
-					limits[i].pl1_max_power,
-					limits[i].pl2_min_power,
-					limits[i].pl2_max_power,
-					limits[i].pl4_power);
-		}
-	}
-}
-
-void variant_devtree_update(void)
-{
-	variant_update_power_limits();
-}