From c581a1841677fd393fb129a87c5e48ec485197b0 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 24 Jul 2013 04:06:37 -0700 Subject: [PATCH] exynos5420: Fix the clock divisor mask. The divisor mask had been set to 0xff, but the bitfield is 4 bits wide. BUG=chrome-os-partner:19420 TEST=Built and booted into RW on pit. A hang still prevents booting, but the EC RW was updated successfully. BRANCH=None Change-Id: Id8a205c80ca2fb0b6f0d86a0c3be4bba9527c0b5 Signed-off-by: Gabe Black Reviewed-on: https://gerrit.chromium.org/gerrit/63188 Reviewed-by: David Hendricks Commit-Queue: Gabe Black Tested-by: Gabe Black --- src/cpu/samsung/exynos5420/clock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/samsung/exynos5420/clock.c b/src/cpu/samsung/exynos5420/clock.c index 694f024ca8..0bc70f1b39 100644 --- a/src/cpu/samsung/exynos5420/clock.c +++ b/src/cpu/samsung/exynos5420/clock.c @@ -359,7 +359,7 @@ void clock_ll_set_ratio(enum periph_id periph_id, unsigned divisor) { struct exynos5420_clock *clk = samsung_get_base_clock(); unsigned shift; - unsigned mask = 0xff; + unsigned mask = 0xf; u32 *reg; switch (periph_id) {