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rockchip: rk3399: change emmc clk to 148.5MHz

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Set aclk_emmc and clk_emmc to 148.5MHz under hs400es mode, which could
improve stability like kernel.

CQ-DEPEND=CL:386527
BUG=chrome-os-partner:54377
BRANCH=none
TEST=build and boot on kevin

Change-Id: Iaa76d3ec1ab999eb317a9ab6c7e3525594b15b57
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e6eb1f5637
Original-Change-Id: If4754d22e83a0f9a029fedca12f26ff5ae8d44e1
Original-Signed-off-by: Ziyuan Xu <xzy.xu@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/386865
Original-Commit-Ready: Julius Werner <jwerner@chromium.org>
Original-Tested-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17790
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Ziyuan Xu 2016-09-18 10:49:52 +08:00 • committed by Patrick Georgi
commit c53cf64e46
1 changed files with 2 additions and 2 deletions
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4
src/soc/rockchip/rk3399/clock.c
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@ -807,8 +807,8 @@ void rkclk_configure_tsadc(unsigned int hz)
void rkclk_configure_emmc(void)
{
int src_clk_div;
int aclk_emmc = 198*MHz;
int clk_emmc = 198*MHz;
int aclk_emmc = 148500*KHz;
int clk_emmc = 148500*KHz;
/* Select aclk_emmc source from GPLL */
src_clk_div = GPLL_HZ / aclk_emmc;