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treewide: Unify Google branding

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Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).

This CL also includes changing Chromium OS to ChromiumOS as well.

BUG=None
TEST=N/A

Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Jon Murphy 2022-06-28 10:36:23 -06:00 • committed by Felix Held
commit c4e90454f4
82 changed files with 126 additions and 126 deletions
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2
src/soc/amd/cezanne/Kconfig
View file

@ -434,7 +434,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD.
certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex

2
src/soc/amd/picasso/Kconfig
View file

@ -466,7 +466,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD.
certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex

2
src/soc/amd/sabrina/Kconfig
View file

@ -454,7 +454,7 @@ config VBOOT_STARTS_BEFORE_BOOTBLOCK
select ARCH_VERSTAGE_ARMV7
help
Runs verstage on the PSP. Only available on
certain Chrome OS branded parts from AMD.
certain ChromeOS branded parts from AMD.
config VBOOT_HASH_BLOCK_SIZE
hex

2
src/soc/intel/common/block/include/intelblocks/cse.h
View file

@ -490,7 +490,7 @@ uint8_t cse_wait_com_soft_temp_disable(void);
/*
* The CSE Lite SKU supports notion of RO and RW boot partitions. The function will set
* CSE's boot partition as per Chrome OS boot modes. In normal mode, the function allows CSE to
* CSE's boot partition as per ChromeOS boot modes. In normal mode, the function allows CSE to
* boot from RW and triggers recovery mode if CSE fails to jump to RW.
* In software triggered recovery mode, the function allows CSE to boot from whatever is
* currently selected partition.

2
src/soc/rockchip/rk3399/spi_bitbang.c
View file

@ -46,7 +46,7 @@ static void set_cs(const struct spi_bitbang_ops *ops, int value)
gpio_set(slave->cs, value);
}
/* Can't use GPIO() here because of bug in GCC version used by Chromium OS. */
/* Can't use GPIO() here because of bug in GCC version used by ChromiumOS. */
static const struct rockchip_bitbang_slave slaves[] = {
[0] = {
.ops = { get_miso, set_mosi, set_clk, set_cs },