diff --git a/src/mainboard/google/brox/variants/caboc/gpio.c b/src/mainboard/google/brox/variants/caboc/gpio.c
index e2127d0ceb..49934999cf 100644
--- a/src/mainboard/google/brox/variants/caboc/gpio.c
+++ b/src/mainboard/google/brox/variants/caboc/gpio.c
@@ -17,7 +17,7 @@ static const struct pad_config override_gpio_table[] = {
 	/* GPP_A17 : [NF4: DISP_MISCC NF6: USB_C_GPP_A17] ==> WWAN_TRANSMIT_OFF(WAN_RF_DISABLE_ODL) */
 	PAD_CFG_GPO(GPP_A17, 1, DEEP),
 	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
-	PAD_CFG_GPO(GPP_A21, 1, DEEP),
+	PAD_CFG_GPO(GPP_A21, 0, DEEP),
 
 	/* GPP_D4 : [NF1: IMGCLKOUT0 NF2: BK4 NF5: SBK4 NF6: USB_C_GPP_D4] ==> WWAN_GPS_XMIT_OFF */
 	PAD_CFG_GPO(GPP_D4, 0, DEEP),
@@ -75,7 +75,7 @@ static const struct pad_config early_gpio_table[] = {
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */
 	PAD_CFG_GPO(GPP_F21, 0, DEEP),
 	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
-	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
 	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */
 	PAD_CFG_GPO(GPP_D19, 0, DEEP),
 
@@ -140,7 +140,7 @@ static const struct pad_config romstage_gpio_table[] = {
 	/* F21 : [NF1: Reserved NF6: USB_C_GPP_F21] ==> WWAN_OFF#(WWAN_FCPO_L) */
 	PAD_CFG_GPO(GPP_F21, 1, DEEP),
 	/* GPP_A21 : [NF1: DDPC_CTRLCLK NF6: USB_C_GPP_A21] ==> WWAN_ASPM_EXIT(WWAN_PERST_L) */
-	PAD_CFG_GPO(GPP_A21, 0, DEEP),
+	PAD_CFG_GPO(GPP_A21, 1, DEEP),
 	/* GPP_D19 : [NF1: I2S_MCLK1_OUT NF6: USB_C_GPP_D19] ==> WWAM_FWUPD#(WWAN_RST_L) */
 	PAD_CFG_GPO(GPP_D19, 0, DEEP),
 
diff --git a/src/mainboard/google/brox/variants/caboc/overridetree.cb b/src/mainboard/google/brox/variants/caboc/overridetree.cb
index 1270765c9a..c70aeca5d1 100644
--- a/src/mainboard/google/brox/variants/caboc/overridetree.cb
+++ b/src/mainboard/google/brox/variants/caboc/overridetree.cb
@@ -252,7 +252,7 @@ chip soc/intel/alderlake
 				.flags = PCIE_RP_LTR | PCIE_RP_AER,
 			}"
 			chip soc/intel/common/block/pcie/rtd3
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
 				register "reset_off_delay_ms" = "20"
 				register "srcclk_pin" = "6"
 				register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL"
@@ -265,7 +265,7 @@ chip soc/intel/alderlake
 			chip drivers/wwan/fm
 				register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F21)"
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D19)"
-				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A21)"
+				register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A21)"
 				register "wake_gpio" = "ACPI_GPIO_IRQ_EDGE_LOW(GPP_E5)"
 				register "add_acpi_dma_property" = "true"
 				use rp4_rtd3 as rtd3dev